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DRAM Integrity Mode
This option sets the type of system memory checking. The settings are:
Setting
Description
Disabled
No error checking or error reporting is done.
Parity
Multibit errors are detected and reported as parity errors. Single-bit errors are
corrected by the chipset. Corrected bits of data from memory are not written
back to DRAM system memory.
ECC
Multibit errors are detected and reported as parity errors. Single-bit errors are
corrected by the chipset and are written back to DRAM system memory.
If a soft (correctable) memory error occurs, writing the fixed data back to
DRAM system memory will resolve the problem. Most DRAM errors are soft
errors.
If a hard (uncorrectable) error occurs, writing the fixed data back to DRAM
system memory does not solve the problem. In this case, the second time the
error occurs in the same location, a Parity Error is reported, indicating an
uncorrectable error.
If ECC is selected, the BIOS automatically enables the System Management
Interface (SMI). If you do not want to enable power management, set the Power
Management/APM option to Disabled and set all Power Management Setup
timeout options to Disabled. To enable power management, set Power
Management /APM to Enabled and set the power management timeout options
as desired.
The Optimal and Fail-Safe settings are Disabled.
DRAM Fast Leadoff
Set this option to Enabled to enable the system memory fast leadoff feature. The settings are
Enabled or Disabled. The Optimal and Fail-Safe settings are Enabled.
DRAM Refresh Type
This option sets the type of system memory refresh. The settings are RAS Only or
CAS/RAS. The Optimal and Fail-Safe settings are CAS/RAS.
DRAM Refresh Queue
Set this option to Enabled to enable the DRAM refresh queue. The settings are Enabled or
Disabled. The Optimal and Fail-Safe settings are Enabled.
