Receiver Description
User Manual
19
STEL-2176
The frame sync stays in the ÒacquisitionÓ state until it
misses this pattern MISS (Bank 1 Register 56
H
) times.
When in the "acquisition" state, the frame sync patterns
are deleted, except the 4 bits identifying the
interleaving parameters. These can be used by the De-
Interleaver to automatically select the De-Interleaving
parameters.
The remaining data, that is all bits between frame syncs,
are formed in 7-table bits symbols and passed to the de-
randomizer.
Derandomizer
The Derandomizer uses a linear feedback shift register
as shown below. It works in GF (128). The delay
elements are initialized at the beginning of each frame
to 7F
H
, 7F
H
and 7F
H
.
3
α
z
-1
7
7
7
Data In
Data Out
WCP 53707.c-10/29/97
z
-1
z
-1
Figure 17. Derandomizer
De-I
nterleaver
This block is a convolutional De-Interleaver, as shown:
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
1
2
3
4
I-2
I-1
1
2
I-4
I-3
I
I-1
I-2
Input
Output
WCP 53704.c-10/28/97
J
Figure 18. De-Interleaver
I and J (Bank 1 Registers 47
H
and 48
H
) are
programmable, however in Level II, the I and J values
are determined by the 4-bit pattern of the frame sync.
A total memory of J
_
(I-1)
_
I/2 is required. The STEL-
2176 has 8K internal memory. Up to 64K memory can
be added externally without any additional logic, as
shown.
Reed-Solomon Decoder
This function decodes Reed-Solomon blocks. Each code
block is 128 (7 bits symbols) long and contains 122
(7Êbits symbols) of data followed by 6 (7 bits symbols)
of checksum. The code blocks are assumed to be coded
according to ITU-T (J.83) Annex B FEC R-S algorithm.
If the decoder fails to decode a code block, the decoder
sets the undecodable flag ÒtrueÓ for this block. This flag
propagates to the STEL-2176 RXDECDFLG output.
In addition, the number of errors in each decodable
block accumulates in Error_cnt[15:0] (Bank 1 Registers
72
H
and 73
H
). This register can be reset by writing a 1 to
CLR_ERR (bit 0 of Bank 1 Register 74
H
).
MPEG Framing
The R-S decoderÕs output is serialized and fed through
the ITU-T (J.83) Annex B MPEG-2 syndrome converter.
The output of the syndrome generator is monitored for
the pattern of 47
H
separated by 1496 bits. When ÒnÓ (n
is a programmable number) successive occurrences of
this pattern are found, MPEG-2 frame sync is declared.
MPEG-2 packets are framed by converting every 8 bits
into one byte.
After declaring successful MPEG-2 frame sync, the
absence of a valid code word at the expected location is
indicated as a packet error.
MPEG-2 framing can be bypassed if so selected. In this
case, the output of the R-S decoder will be reformed
into bytes starting at the beginning of each frame.
Output Clock Block
The output clock block functionally the same as the
Annex A output clock block. However, the gaps
between data bytes occur due to eliminating the R-S
checksum symbols, the frame sync information, and the
bits that were added to support Viterbi decoding.
