Receiver Description
STEL-2176
16
User Manual
Frame Sync
The frame sync receives symbols from the mapper.
Each symbol represents 4, 6 or 8 bits for 16 QAM, 64
QAM, and 256 QAM respectively. These bits are
collected into bytes. For 16 QAM, every two symbols
are converted into one byte. For 64 QAM, every 4
symbols to are converted into 3 bytes, and for 256 QAM
each symbol gives one byte..
Once bytes are formed, the frame sync block looks for a
sequence of fixed byte values separated by 203 bytes of
data.
47
H
(203 bytes) B8
H
(203 bytes) 47
H
(203 bytes) 47
H
(203
bytes) 47
H
. . .
47
H
. . .
47
H
. . . .
47
H
. .
47
H
. . .
47
H
. . .
B8
H
. . .
When the frame sync finds this pattern HIT (Block 1
Register 55
H
) times, the frame sync block declares
ÒacquisitionÓ and starts feeding the bytes to the De-
Interleaver. The frame sync stays in the ÒacquisitionÓ
state until it misses this pattern MISS (Block 1 Register
56
H
) times.
De-I
nterleaver
This block is a convolutional De-Interleaver, as shown:
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
1
2
3
4
I-2
I-1
1
2
I-4
I-3
I
I-1
I-2
Input
Output
WCP 53704.c-10/28/97
J
Figure 12. De-Interleaver
I and J are programmable (Block 1 Registers 47
H
and
48
H
).
A total memory of J
_
(I-1)
_
I/2 is required. The STEL-
2176 has 8K internal memory. Up to 64K memory can
be added externally without any additional logic, as
shown.
Reed-Solomon Decoder
This function decodes Reed-Solomon blocks. Each code
block is 204 bytes long and contains 188 bytes of data
followed by 16 bytes of checksum. The code blocks are
assumed to be coded according to ITU-T (J.83) Annex A
FEC shortened R-S algorithm.
If the decoder fails to decode a code block, the decoder
sets the undecodable flag ÒtrueÓ for this block. This flag
propagates to the STEL-2176 output as RXDECDFLG.
In addition, the number of errors in each decodable
block accumulates in Error_cnt[15:0] (Block 1 Registers
72
H
and 73
H
). This register can be reset by writing a 1 to
CLR_ERR (bit 0 of Block 1 Register 74
H
).
De-
R
andomizer
The de-randomizer is exactly the same as the
randomizer described by the ITU-T (J.83) Annex A
standard.
Output Clock Block
The function of the output clock block is to evenly
distribute the output receive data of the STEL-2176 and
to eliminate gaps caused by the FEC subsystem. The
output of the Reed-Solomon decoder is 188 bytes of
data for every 204 input bytes. Therefore, there is a gap
of 16 bytes where the checksum information is
removed.
The STEL-2176 output can send the received data in
bytes on an 8-bit wide buss, or in bits on a single line as
shown in Downstream Output Timing Diagrams
(Figure 19 through Figure 21). Selecting between
ÒbytewiseÓ versus ÒbitwiseÓ can be done by setting
Serial Mode (bit 0 of Bank 1 Register 69
H
) to 1.
ANNEX B
The ITU-T (J.83) Annex B FEC subsystem consists of the
following blocks:
Trellis
Coded
De-modulator
De-Interleaver
Reed-Solomon
Decoder
MPEG-2
Framing
Frame
Sync
De-Randomizer
I,Q from
Adaptive
Equalizer
To Output Clock
WCP 53705.c-10/28/97
Figure 13. ITU-T (J.83) Annex B FEC Subsystem
