Transmitter Description
User Manual
59
STEL-2176
BIT CLOCK SYNCHRONIZATION
WCP 53826.c-12/5/97
TXACLK
TXBITCLK
tCO
TXTCLK
TXCLKEN
2 (N +1) BPSK
(N +1) QPSK
N +1
2
16QAM
n = Odd
N +2
2
16QAM
n = Even
tCESU
See Note 2
See Note 1
tCO
Note 1: TXBITCLK will be forced high on the second rising edge of CLK following the rising edge of TXTCLK.
Note 2: The period of time that TXBITCLK is high is measured in cycles of CLK (e.g. (N + 1) in QPSK). "N" is a
12-bit binary number formed by taking bits 3-0 of Block 2 Register 39
H
as the MSB's and taking bits 7-0 of
Block 2 Register 29
H
as the LSB's. The TXBITCLK low period is the same except for 16QAM when "N" is
even in which case the low period is (N/2) yielding the correct TXBITCLK period but not a perfect
squarewave.
Table 53. Bit Clock Synchronization AC Characteristics
(V
DD
= 3.3 V
±
10%, V
SS
= 0 V, T
a
= Ð40
°
to 85
°
C)
Symbol
Parameter
Min.
Nom.
Max.
Units
Conditions
t
CO
Clock to TXBITCLK, TXSYMPLS, TXDATAENO, or
TXACLK edge
2
nsec
t
CESU
Clock Enable (TXCLKEN to TXTCLK Setup)
3
nsec