Intel
®
Xeon
®
Processor Specification Update
55
Specification Clarifications
The RDMSR and WRMSR instructions read and write the time-stamp counter, treating the
time-stamp counter as an ordinary MSR (address 10H). In the Pentium 4, Intel Xeon, and P6 family
processors, all 64-bits of the time-stamp counter are read using RDMSR (just as with RDTSC).
When WRMSR is used to write the time-stamp counter on processors before family [0FH], models
[03H, 04H]: only the low order 32-bits of the time-stamp counter can be written (the high-order 32
bits are cleared to 0). For family [0FH], models [03H, 04H]: all 64 bits are writeable.
15.10.9
Counting Clocks
The count of cycles, also known as clockticks, forms a the basis for measuring how long a program
takes to execute. Clockticks are also used as part of efficiency ratios like cycles per instruction
(CPI). Processor clocks may stop ticking under circumstances like the following:
•
The processor is halted when there is nothing for the CPU to do. For example, the processor
may halt to save power while the computer is servicing an I/O request. When Hyper-Threading
Technology is enabled, both logical processors must be halted for performance-monitoring
counters to be powered down.
•
The processor is asleep as a result of being halted or because of a power-management scheme.
There are different levels of sleep. In the some deep sleep levels, the time-stamp counter stops
counting.
There are three ways to count processor clock cycles to monitor performance. These are:
•
Non-halted clockticks
— Measures clock cycles in which the specified logical processor is
not halted and is not in any power-saving state. When Hyper-Threading Technology is
enabled, this these ticks can be measured on a per-logical-processor basis.
•
Non-sleep clockticks
— Measures clock cycles in which the specified physical processor is
not in a sleep mode or in a power-saving state. These ticks cannot be measured on a
logical-processor basis.
•
Time-stamp counter
— Some processor models permit clock cycles to be measured when the
physical processor is not in deep sleep (by using the time-stamp counter and the RDTSC
instruction). Note that such ticks cannot be measured on a per-logical-processor basis. See
Section 10.8 for detail on processor capabilities.
The first two methods use performance counters and can be set up to cause an interrupt upon
overflow (for sampling). They may also be useful where it is easier for a tool to read a performance
counter than to use a time stamp counter (the timestamp counter is accessed using the RDTSC
instruction).
For applications with a significant amount of I/O, there are two ratios of interest:
•
Non-halted CPI
— Non-halted clockticks/instructions retired measures the CPI for phases
where the CPU was being used. This ratio can be measured on a logical-processor basis when
Hyper-Threading Technology is enabled.
•
Nominal CPI
— Time-stamp counter ticks/instructions retired measures the CPI over the
duration of a program, including those periods when the machine halts while waiting for I/O.
15.10.9.3
Incrementing the Time-Stamp Counter
The time-stamp counter increments when the clock signal on the system bus is active and when the
sleep pin is not asserted. The counter value can be read with the RDTSC instruction.
The time-stamp counter and the non-sleep clockticks count may not agree in all cases and for all
processors. See Section 10.8 for more information on counter operation.
