Intel SL6NQ - Xeon 2.4 GHz/533MHz/512 KB CPU Processor 2.4GHz Specification Download Page 52

Page: 52 / 56

Intel

Xeon

Processor Specification Update

Specification Changes

ECX [Bits]

Descriptions of Feature Flag Value

Context ID.

A value of ‘1’ indicates the L1 data cache mode can be set to either adaptive

mode or shared mode. A value of ‘0’ this feature is not supported. See definition of the
IA32_MISC_ENABLE MSR Bit 24 (L1 Data Cache Context Mode) for more details.

Summary of Contents for SL6NQ - Xeon 2.4 GHz/533MHz/512 KB CPU Processor 2.4GHz

Page 1: ...Document Number 249678 057 Notice The Intel Xeon processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characteri...

Page 2: ...must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for...

Page 3: ...on Update 3 Contents Revision History 5 Preface 9 Identification Information 10 Mixed Steppings in DP Systems 18 Summary Table of Changes 20 Errata 27 Specification Changes 51 Specification Clarificat...

Page 4: ...4 Intel Xeon Processor Specification Update...

Page 5: ...test errata status Added Documentation Changes P1 P5 November 2001 009 Added errata P36 and P37 Added Documentation Change P6 Updated Summary Tables with latest errata and documentation changes Decemb...

Page 6: ...Deleted old Documentation Changes Deleted old Specification Changes Added new Processor Intel Xeon Processor with 533 MHz Front Side Bus Added new processor with Processor Signature 0F27h C1 Step Adde...

Page 7: ...dated erratum P65 November 2003 034 Added Specification Clarification P3 December 2003 035 Added new Processor Intel Xeon Processor with 2 MB L3 Cache with Processor Signature 0F25H M0 Stepping Februa...

Page 8: ...ded s spec SL8TJ March 2006 053 Added S specs SL8TK SL8TL SL8SE and SL8TH April 2006 054 Updated Summary Table of Changes Updated the Software Developer Manual Name October 2006 055 Made changes to th...

Page 9: ...rocessor s behavior to deviate from published specifications Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on a...

Page 10: ...INT mPGA Package Figure 1 Top Side Processor Marking Figure 2 Bottom Side Processor Marking Intel Xeon i m 01 D0096109 0032 2D Matrix OR Dynamic Laser Mark Area ATPO Mark 8 Characters Serial Number M...

Page 11: ...oser INT mPGA Package and 604 pin Fc mPGA2 Package Figure 3 Top Side Processor Marking Figure 4 Bottom Side Processor Marking Intel Xeon i m c 02 2D Matrix Includes ATPO and Serial Number front end ma...

Page 12: ...voltage Family1 1 The Family corresponds to bits 11 8 of the EDX register after RESET bits 11 8 of the EAX register after the Processor Signature instruction is executed with a 1 in the EAX register...

Page 13: ...0 603 pin micro PGA interposer with 31 mm OLGA rev 2 0 1 2 4 SL56N C1 0F0Ah 1 70 400 256 KB B0 603 pin micro PGA interposer with 31 mm OLGA rev 2 0 1 4 SL56H C1 0F0Ah 1 70 400 256 KB B0 603 pin micro...

Page 14: ...kage SL6JZ C1 0F27H 2 20 400 512 KB 01 603 pin micro PGA interposer with 35 mm FC BGA package 2 SL6EP C1 0F27H 2 40 400 512 KB 01 603 pin micro PGA interposer with 35 mm FC BGA package SL6K2 C1 0F27H...

Page 15: ...7 SL6W3 SL6YS D1 0F29H 1 80 400 512 KB 01 603 pin micro PGA interposer with 35 mm FC BGA package 3 2 SL6W6 SL6YT D1 0F29H 2 400 512 KB 01 603 pin micro PGA interposer with 35 mm FC BGA package 3 2 SL...

Page 16: ...533 512 KB 01 604 pin micro PGA interposer with 42 5 mm FC PGA2 package 2 SL73N SL72F M0 0F25H 2 80 533 512 KB 01 604 pin micro PGA interposer with 42 5 mm FC PGA2 package 2 SL73P SL72G M0 0F25H 3 06...

Page 17: ...th 533 MHz Front Side Bus 6 These parts have a VID of 1 525V 7 These parts are the Low Voltage Intel Xeon Processor 8 These parts are the Intel Xeon Processor with 1 MB L3 Cache 9 These parts are the...

Page 18: ...n customers may wish to perform validation of system configurations with mixed frequency or cache sizes and that those efforts are an acceptable option to our customers customers would be fully respon...

Page 19: ...e Intel Xeon Processor Intel Xeon Processor with 1 MB L3 cache and Intel Xeon Processor with 2 MB L3 cache 3 This only applies to 0F25h stepping without L3 cache 4 This only applies to 0F25h stepping...

Page 20: ...Intel Xeon processor substrate AP APIC related erratum Change bar to left of table row indicates this item is either new or modified from the previous version of this document Each Specification Updat...

Page 21: ...ntel Pentium processor Extreme Edition and Intel Pentium D processor on 65 nm process AB Intel Pentium 4 processor on 65 nm process AC Intel Celeron Processor in 478 Pin Package AG Dual Core Intel Xeo...

Page 22: ...X X X X X X X No Fix Debug mechanisms may not function as expected P12 X Fixed Processor may live lock if PDEs or PTEs are in UC space P13 X Fixed Thermal status log bit may not be set when the therma...

Page 23: ...ng event selection control ESCR MSR P35 X X X Fixed Livelock may occur when bus parking is disabled P36 X X X Fixed CR2 May be incorrect or an incorrect page fault error code may be pushed on to stack...

Page 24: ...he test access port TAP is sensitive to low clock edge rates and prone to noise coupling onto TCK s rising or falling edges P59 X X X X X X X No Fix Disabling a local APIC disables both logical proces...

Page 25: ...dating the page table entry P76 X X X Plan Fix A timing marginality in the Arithmetic Logic Unit ALU may cause indeterminate behavior P77 X X X X X X X No Fix With Trap Flag TF asserted FP instruction...

Page 26: ...d to processor signature instruction feature Flags IA32_MISC_Enable registers Specification Clarifications No SPECIFICATION CLARIFICATIONS P1 Maximum ITCC specification correction P2 Specification Cla...

Page 27: ...ted see the Summary Table of Changes P3 Invalid opcode 0FFFh requires a ModRM byte Problem Some invalid opcodes require a ModRM byte and other following bytes while others do not The invalid opcode 0F...

Page 28: ...cause the other half to increment When a performance counter is written and the event counter for the event being monitored is non zero the performance counter will be incremented by the value on tha...

Page 29: ...recover from the error In the situations described below the processor does not report and or recover from the error s as intended When a transaction is deferred during the snoop phase and subsequentl...

Page 30: ...he SMM handler If the SMM handler is successfully completed it will attempt to restart the I O instruction but will not have the correct machine state due to the call to the MCE handler This can lead...

Page 31: ...wing conditions occur 1 An FLD instruction signals a stack overflow or underflow 2 the FLD instruction splits a page boundary or a 64 byte cache line boundary 3 the instruction matches a debug registe...

Page 32: ...leared set to 0 although the thermal control circuit is active Workaround None at this time Status For the steppings affected see the Summary Table of Changes P14 Processor may timeout waiting for a d...

Page 33: ...whose instruction bytes are in UC space and which takes an exception 16 FP error exception The processor stalls trying to fetch the bytes of the faulting FP instruction and those following it This pro...

Page 34: ...nges P22 System bus interrupt messages without data and which receive a Hard failure response may hang the processor Problem When a system bus agent processor or chipset issues an interrupt transactio...

Page 35: ...issue a BIL snoop to the deferred processor to eliminate the failure conditions Status For the steppings affected see the Summary Table of Changes P25 Multiprocessor boot protocol may not complete wit...

Page 36: ...re that the page fault handler restarts program execution at the faulting instruction after correcting the paging problem Status For the steppings affected see the Summary Table of Changes P29 Write c...

Page 37: ...s mode and writes are made to DR6 and DR7 the processor should block writes to the reserved bit locations Due to this erratum the processor may not block these writes This may result in invalid data i...

Page 38: ...truction but the value of CR2 and the error code pushed on the stack are reflective of the speculative state Intel has not observed this erratum with commercially available software Implication When t...

Page 39: ...which HT Technology enabled processors are executing extensive self modifying code and branch trace messages are enabled on at least one logical processor the system may hang In this scenario a proce...

Page 40: ...or will hang Workaround If use of the on demand mode of the processor s TCC is desired in conjunction with STPCLK modulation then assure that STPCLK is not asserted at a 12 5 duty cycle Status For the...

Page 41: ...em Re mapping the APIC base address from its default can cause conflicts with either I O or special cycle bus transactions Implication Either I O or special cycle bus transactions can be redirected to...

Page 42: ...bled via power on configuration it should return a value of 51h in EAX 15 8 to indicate that the instruction translation lookaside buffer ITLB has 128 entries On a processor with HT Technology enabled...

Page 43: ...tinue single step execution after the first breakpoint Problem ITP will not continue in single step execution after the first software breakpoint ITP is unable to reset the resume flag RF bit in the E...

Page 44: ...ion If this erratum occurs the processor will go into and out of the sleep state without making forward progress since the logical processor will not be able to service any pending event This erratum...

Page 45: ...cesses are vulnerable The vulnerability of the alignment for any given fault is dependent on the state of other circuitry in the processor Additionally a third fault from an access that occurs sequent...

Page 46: ...y available software or system Workaround None at this time Status For the steppings affected see the Summary of Table of Changes P68 Modified cache line eviction from L2 cache may result in write bac...

Page 47: ...f this erratum occurs the system may hang Workaround The pages should not be mapped as either UC or WC and WB at the same time Status For the steppings affected see the Summary of Table of Changes P72...

Page 48: ...software Workaround The guidelines in the IA 32 Intel Architecture Software Developer s Manual should be followed Status For the steppings affected see the Summary Table of Changes P76 A timing margin...

Page 49: ...s integer multiple of the corresponding record sizes as recommended in the IA 32 Intel Architecture Software Developer s Manual Volume 3 Status For the steppings affected see the Summary Table of Chan...

Page 50: ...itten an interrupt may be taken on the new interrupt vector even if the mark bit is set Implication An interrupt may immediately be generated with the new vector when a LVT entry is written even if th...

Page 51: ...hanged from Reserved to the following definition IA32_MISC_ENABLE Miscellaneous Enables Register bit 24 MSR Address 01A0h Accessed as a Qword Default Value High Dword XXXX XXXXh Low Dword XXXX XXXX XX...

Page 52: ...criptions of Feature Flag Value 10 Context ID A value of 1 indicates the L1 data cache mode can be set to either adaptive mode or shared mode A value of 0 this feature is not supported See definition...

Page 53: ...sheet Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Datasheet and Intel Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3 20 GHz Datasheet Current table and note Note 7 The m...

Page 54: ...odels 03H and higher the time stamp counter increments at a constant rate That rate may be set by the maximum core clock to bus clock ratio of the processor or may be set by the frequency at which the...

Page 55: ...power saving state When Hyper Threading Technology is enabled this these ticks can be measured on a per logical processor basis Non sleep clockticks Measures clock cycles in which the specified physi...

Page 56: ...46 htm The Documentation Changes listed in this section apply to the following documents Intel Xeon Processor at 1 40 GHz 1 50 GHz 1 70 and 2 GHz Datasheet Order Number 249665 Intel Xeon Processor wit...

Search results

Summary of Contents for SL6NQ - Xeon 2.4 GHz/533MHz/512 KB CPU Processor 2.4GHz

Reviews:

Related manuals for SL6NQ - Xeon 2.4 GHz/533MHz/512 KB CPU Processor 2.4GHz

Brands by name

Popular brands

Intel SL6NQ - Xeon 2.4 GHz/533MHz/512 KB CPU Processor 2.4GHz, Specification

Search results

Summary of Contents for SL6NQ - Xeon 2.4 GHz/533MHz/512 KB CPU Processor 2.4GHz

Reviews:

Related manuals for SL6NQ - Xeon 2.4 GHz/533MHz/512 KB CPU Processor 2.4GHz

Brands by name

Popular brands