40
Intel
®
Xeon
®
Processor Specification Update
Errata
P42
Machine check exception (MCE) observed on DP platforms
Problem:
A system bus address parity error may be signaled if two processors run at odd core frequency to
system Bus-ratios (17:1, 19:1, etc.) on DP processor platforms. This address parity error signaling
issue does not occur if the processors run at even bus-ratios.
Implication:
A MCE may be observed on DP platforms.
Workaround:
The system BIOS should ensure that processors run at even core frequency to system bus-ratios
(16:1, 18:1, etc.).
Status:
For the steppings affected, see the
Summary Table of Changes
.
P43
BPM[5:3]# VIL does not meet specification
Problem:
The VIL for BPM[5:3]# is specified as 0.9 * GTLREF [V]. Due to this erratum the VIL for these
signals is 0.9 * GTLREF -.100 [V].
Implication:
The processor requires a lower input voltage than specified to recognize a low voltage on the
BPM[5:3]# signals.
Workaround:
When intending to drive the BPM[5:3]# signals low, ensure that the system provides a voltage
lower than (0.9 * GTLREF -.100 [V]).
Status:
For the steppings affected, see the
Summary Table of Changes
.
P44
Processor may hang under certain frequencies and 12.5% STPCLK# duty
cycle
Problem:
If a system deasserts STPCLK# at a 12.5% duty cycle, and the processor is running below 2 GHz,
and the processor thermal control circuit (TCC) on-demand clock modulation is active, the
processor may hang. This erratum does not occur under the automatic mode of the TCC.
Implication:
When this erratum occurs, the processor will hang.
Workaround:
If use of the on-demand mode of the processor's TCC is desired in conjunction with STPCLK#
modulation, then assure that STPCLK# is not asserted at a 12.5% duty cycle.
Status:
For the steppings affected, see the
Summary Table of Changes
.
P45
System may hang if a fatal cache error causes bus write line (BWL)
transaction to occur to the same cache line address as an outstanding bus
read line (BRL) or bus read-invalidate line (BRIL)
Problem:
A processor internal cache fatal data ECC error may cause the processor to issue a bus write line
(BWL) transaction to the same cache line address as an outstanding bus read line (BRL) or bus
read-invalidate line (BRIL). As it is not typical behavior for a single processor to have a BWL and
a BRL/BRIL concurrently outstanding to the same address, this may represent an unexpected
scenario to system logic within the chipset.
Implication:
The processor may not be able to fully execute the machine check handler in response to the fatal
cache error if system logic does not ensure forward progress on the system bus under this scenario.
Workaround:
System logic should ensure completion of the outstanding transactions. Note that during recovery
from a fatal data ECC error, memory image coherency of the BWL with respect to BRL/BRIL
transactions is not important. Forward progress is the primary requirement.
Status:
For the steppings affected, see the
Summary Table of Changes
.
P46
L2 cache may contain stale data in the exclusive state
Problem:
If a cache line (A) is in Modified (M) state in the write-combining (WC) buffers and in the Invalid
(I) state in the L1 cache and it's adjacent sector (B) is in the Invalid (I) state and the following
scenario occurs:
