54
Intel
®
Xeon
®
Processor Specification Update
Specification Clarifications
15.8
Time-Stamp Counter
The IA-32 architecture (beginning with the Pentium
®
processor) defines a time-stamp counter
mechanism that can be used to monitor and identify the relative time occurrence of processor
events. The counter’s architecture includes the following components:
•
TSC flag
—
A feature bit that indicates the availability of the time-stamp counter. The counter
is available in an IA-32 processor implementation if the function CPUID.1:EDX.TSC[bit 4] =
1.
•
IA32_TIME_STAMP_COUNTER MSR
(called TSC MSR in P6 family and Pentium
processors) —
The MSR used as the counter.
•
RDTSC instruction
—
An instruction used to read the time-stamp counter.
•
TSD flag
—
A control register flag is used to enable or disable the time-stamp counter
(enabled if CR4.TSD[bit 2] = 1).
The time-stamp counter (as implemented in the P6 family, Pentium, Pentium M, Pentium 4, and
Intel
®
Xeon
®
processors) is a 64-bit counter that is set to 0 following a RESET of the processor.
Following a RESET, the counter will increment even when the processor is halted by the HLT
instruction or the external STPCLK# pin. Note that the assertion of the external DPSLP# pin may
cause the time-stamp counter to stop.
Members of the processor families increment the time-stamp counter differently:
•
For Pentium M processors (family [06H], models [09H, 0DH]); for Pentium 4 processors,
Intel Xeon processors (family [0FH], models [00H, 01H, or 02H]); and for P6 family
processors: the time-stamp counter increments with every internal processor clock cycle. The
internal processor clock cycle is determined by the current core-clock to bus-clock ratio. Intel
SpeedStep
®
technology transitions may also impact the processor clock.
•
For Pentium 4 processors, Intel Xeon processors (family [0FH], models [03H and higher]): the
time-stamp counter increments at a constant rate. That rate may be set by the maximum
core-clock to bus-clock ratio of the processor or may be set by the frequency at which the
processor is booted. The specific processor configuration determines the behavior. Constant
TSC behavior ensures that the duration of each clock tick is uniform and supports the use of
the TSC as a wall clock timer even if the processor core changes frequency. This is the
architectural behavior moving forward.
Note:
To determine average processor clock frequency, Intel recommends the use of Performance
Monitoring logic to count processor core clocks over the period of time for which the average is
required. See Section 15.10.9 and Appendix A in this manual for more information.
The RDTSC instruction reads the time-stamp counter and is guaranteed to return a monotonically
increasing unique value whenever executed, except for a 64-bit counter wraparound. Intel
guarantees that the time-stamp counter will not wraparound within 10 years after being reset. The
period for counter wrap is longer for Pentium 4, Intel Xeon, P6 family, and Pentium processors.
Normally, the RDTSC instruction can be executed by programs and procedures running at any
privilege level and in virtual-8086 mode. The TSD flag allows use of this instruction to be
restricted to programs and procedures running at privilege level 0. A secure operating system
would set the TSD flag during system initialization to disable user access to the time-stamp
counter. An operating system that disables user access to the time-stamp counter should emulate
the instruction through a user-accessible programming interface.
The RDTSC instruction is not serializing or ordered with other instructions. It does not necessarily
wait until all previous instructions have been executed before reading the counter. Similarly,
subsequent instructions may begin execution before the RDTSC instruction operation is
performed.
