manualshive.com logo in svg

Intel SE7505VB2, Specification

Share
Download
Intel SE7505VB2 Specification Download Page 49

Intel® Server Board SE7505VB2 

SE7505VB2 ACPI Implementation 

The power button input (SW2#) provides PWRBTN_IN signal to the sIO. The power button input 
behaves differently depending on whether or not the operating system supports ACPI.  

Power Button Off to On: 

The sIO may be configured to generate wakeup events for several 
different system events: Wake on LAN*, PCI Power Management 
Interrupt, and Real Time Clock Alarm are examples of these 
events. Since the processors are not executing, the BIOS does not 
participate in this sequence. The sIO provides ONSTL# signal to 
the power supply. The ICH4 and receive power good and reset and 
then transition to an ON state.  

Power Button On to Off 
(Legacy): 

The ICH4 is configured to generate an SMI due to a power button 
event. The BIOS services this SMI and sets the state of the 
machine in the ICH4 and sIO to the OFF state.  

Power Button On to Off 
(ACPI): 

If an ACPI operating system is loaded, the power button switch 
generates a request (via SCI) to the OS to shutdown the system. 
The OS retains control of the system and determines what sleep 
state (if any) the system transitions to.  

Reset Button: 

The reset button will generate a hard reset to the system. 

NMI Button: 

The NMI button will force an NMI to the processors. 

7.1.2 

Wake up Sources (ACPI and Legacy) 

The baseboard is capable of wake up from several sources under a non-ACPI configuration, 
such as when the operating system does not support ACPI. The wake up sources are defined in 
the following table.  

Table 19. Supported Wake Events 

Wake Event 

Supported via ACPI 

(by sleep state) 

Supported Via Legacy Wake 

Power Button 

Always wakes system 

Always wakes system 

Ring indicate from serial1 

S1, S4, S5 

S5 

Ring indicate from serial2 

S1, S4, S5 

S5 

PME from PCI 32/33 

S1, S4, S5 

S5 

PME from PCI secondary 64/100 

S1, S4, S5 

S5 

PME from primary PCI 64/66 

S1, S4, S5 

S5 

RTC Alarm 

S1, S4 

No 

Mouse S1 

No 

Keyboard S1 

No 

USB S1 

No 

 
Under ACPI, the operating system programs the ICH4 and sIO to wake up on the desired event, 
but in legacy mode, the BIOS enables/disables wake up sources based on an option in BIOS 
Setup. The operating system or a driver must clear any pending wake up status bits in the 
associated hardware (such as the Wake on LAN status bit in the LAN application specific 
integrated circuit (ASIC), or PCI Power Management Event (PME) status bit in a PCI device. 
The legacy wake up feature is disabled by default.  

Revision 1.2 

 

 

 

Intel part number C32194-002 

49

Summary of Contents for SE7505VB2

Page 1: ...Intel Server Board SE7505VB2 Technical Product Specification Intel part number C32194 002 Revision 1 2 April 2004 Enterprise Platforms and Services Marketing ...

Page 2: ...y 2003 1 0 Initial Release March 2003 1 1 Added memory cooling duct information added section on BIOS event log incorporated Technology Leadership terminology and corrected miscellaneous minor technical details April 2004 1 2 New graphics for Mechanical Changes Revision 1 2 Intel part number C32194 002 ii ...

Page 3: ...ended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibiliti...

Page 4: ...er I O 28 3 3 1 GPIOs 29 3 3 2 Serial Ports 29 3 3 3 BIOS Flash 30 4 Clock Generation and Distribution 31 5 PCI I O Subsystem 33 5 1 PCI Subsystem 33 5 1 1 P32 A 32 bit 33 MHz PCI Subsystem 33 5 1 2 P64 B and P64 C 64 bit 100 or 66 MHz PCI Subsystem 34 5 2 Serial ATA Controller 35 5 3 Video Controller 36 5 3 1 Video Modes 37 5 3 2 Video Memory Interface 37 5 3 3 Host Bus Interface 38 5 4 Network I...

Page 5: ...ocket 52 8 4 I2 C Header 55 8 5 PCI Slot Connector 55 8 6 AGP 3 0 Pro50 Connector 58 8 7 Front Panel Connector 59 8 8 VGA Connector 59 8 9 NIC Connector 60 8 10 IDE Connector 60 8 11 SATA Connector 61 8 12 USB Connector 62 8 13 Floppy Connector 63 8 14 Serial Port Connector 63 8 15 Keyboard and Mouse Connector 64 8 16 Miscellaneous Headers 64 8 16 1 Fan Header 64 8 16 2 Intrusion Cable Connector 6...

Page 6: ...cations 96 12 2 1 Power Timing 96 12 2 2 Voltage Recovery Timing Specifications 99 13 Product Regulatory Compliance 100 13 1 1 Product Safety Compliance 100 13 1 2 Product EMC Compliance 100 13 1 3 Mandatory Standard Certifications Registration Declarations 100 13 1 4 Other Product Mandatory Regulations to Consider due to new Emerging International Requirements 101 13 1 5 Important Product Regulat...

Page 7: ...rd SE7505VB2 Table of Contents 13 3 Replacing the Back up Battery 102 14 Mechanical Specifications 104 Glossary 106 Reference Documents 108 Index Error Bookmark not defined Revision 1 2 Intel part number C32194 002 vii ...

Page 8: ...igure 6 Interrupt Routing Diagram ICH4 Internal 42 Figure 7 Interrupt Routing Diagram 43 Figure 8 The Board PCI Interrupt Mapping Diagram 44 Figure 9 Hardware Monitoring 47 Figure 10 System Recovery and Update Jumpers J4J1 66 Figure 11 BIOS Recovery Jumper 92 Figure 12 Output Voltage Timing 97 Figure 13 Turn on off Timing 98 Figure 14 Intel Server Board SE7505VB2 Mechanical Drawing 104 Figure 15 B...

Page 9: ...ting Sharing 40 Table 17 Interrupt Definitions 41 Table 18 Monitored Components 45 Table 19 Supported Wake Events 49 Table 20 Power Connector Pin out J9B1 50 Table 21 Auxiliary Signal Connector J7K1 50 Table 22 Auxiliary CPU Power Connector Pin out J9K1 50 Table 23 DIMM Connectors J9H1 J9J1 J9H2 J9J2 51 Table 24 Socket 604 Processor Socket Pin out U8C1 U5C1 52 Table 25 SCSI HDD Header Pin out J3K2...

Page 10: ...on Cable Connector Pin Out 65 Table 45 System Recovery and Update Jumper Options 66 Table 46 Keyboard Commands 68 Table 47 On Screen Options 69 Table 48 Menu Selection Bar 69 Table 49 Main Menu 70 Table 50 Primary Secondary Master Slave Submenu 71 Table 51 Advanced Menu 72 Table 52 I O Device Configuration Submenu 74 Table 53 On Board Device Submenu 76 Table 54 PCI Configuration Submenu 77 Table 5...

Page 11: ...93 Table 69 Absolute Maximum Ratings 94 Table 70 The Board Power Budget 95 Table 71 The Board Power Supply Voltage Specification 96 Table 72 Voltage Timing Parameters 97 Table 73 Turn On Off Timing 98 Table 74 Transient Load Requirements 99 Revision 1 2 Intel part number C32194 002 xi ...

Page 12: ...List of Tables Intel Server Board SE7505VB2 This page intentionally left blank Revision 1 2 Intel part number C32194 002 xii ...

Page 13: ...l detail of some of the board s functional sub systems This document is intended to be the technical reference for this board Updates to this document will be made via the Specification Update published monthly from the date of product launch Please refer to the Intel Server Board SE7505VB2 support website for any updates to this document http support intel com support motherboards server se7505vb...

Page 14: ...oller P64H2 64 bit I O Hub ICH4 I O controller FWH Firmware Hub Glue4 PAL Support for up to four DDR266 compliant ECC DDR DIMMs providing up to 8 GB of memory Three separate and independent PCI buses Segment A Two PCI 32 bit 33 MHz 5 V connectors supporting full length PCI add in cards and three embedded devices 2D 3D graphics controller ATI Rage XL video controller with 8 MB of SDRAM One Intel 10...

Page 15: ... ports with an additional internal header providing one optional USB ports for front panel support Two IDE connectors supporting up to four ATA 100 compatible devices Support for up to four system fans and two processor fans SSI compliant connectors for SSI interface support front panel and power connectors The following figure below shows the functional blocks of the server board and the plug in ...

Page 16: ...E7505VB2 supports one or two processors in the 604 pin FCPGA package When two processors are installed all processors must be of identical revision core voltage and bus core speed When only one processor is installed it should be in the socket labeled CPU1 and the other socket must be empty The support circuitry on the server board consists of the following Dual 604 pin processor sockets supportin...

Page 17: ...is supported Processors run at a fixed speed and cannot be programmed to operate at a lower or higher speed The processor information is read at every system power on Note The processor speed is the processor power on reset default value No manual processor speed setting options exist either in the form of a BIOS setup option or jumpers 3 1 1 3 Processor Module Presence Detection Logic is provided...

Page 18: ... are supported by design but only fully qualified DIMMs will be supported on the board The minimum supported DIMM size is 128 MB Therefore the minimum main memory configuration is 1 x 128 MB or 128 MB The largest size DIMM supported is a 2 GB registered DDR266 ECC DIMM based on 512 megabit technology Therefore the maximum main memory configuration is 4 x 2 GB or 8 GB Only registered DDR266 complia...

Page 19: ...MM and memory configurations must adhere to the following DDR266 ECC registered DDR DIMM modules DIMM organization x72 ECC Pin count 184 DIMM capacity 128 MB 256 MB 512 MB 1 GB 2GB DIMMs Serial PD JEDEC Rev 2 0 Voltage options 3 3 V VDD VDDQ Interface SSTL2 3 1 2 3 Memory Cooling The SE7505VB2 server board supports DDR memory in a variety of sizes and densities see Table 4 Due to the specific orie...

Page 20: ...rd SE7505VB2 Table 2 Memory Bank Labels Memory DIMM Bank J9H1 DIMM 1A J9H2 DIMM 1B 1 J9J1 DIMM 2A J9J2 DIMM 2B 2 Bank 2 J9H1 J9H2 J9J1 J9J2 1A 2A 1B 2B Bank 1 Figure 3 Memory Bank Label Definition Revision 1 2 Intel part number C32194 002 20 ...

Page 21: ...f the ECC bits to data bits is the same as the previous example 16 128 vs 8 64 the longer ECC word allows for a correction and detection algorithm that is more efficient 3 2 The Intel E7505 Chipset The Intel Server Board SE7505VB2 is designed around the Intel E7505 chipset The chipset provides an integrated I O bridge and memory controller and a flexible I O subsystem core PCI PCI X This is target...

Page 22: ...16 bits wide and operates at 66 MHz with 512MT s providing over 1 GB per second of bandwidth All I O for the board including PCI and PC compatible I O is directed through the MCH and then through either the P64H2 or the ICH4 provided PCI buses The ICH4 provides one 32 bit 33 MHz PCI bus hereafter called P32 A The P64H2 provides one 64 bit 100 MHz PCI X bus hereafter called P64 B and one 64bit 66MH...

Page 23: ...512Mbit 128M x 4 36 2 4 13 2 12 3 2 2 Memory Controller Hub MCH The MCH is a 1005 ball FC BGA device and uses the proven components of previous generations like the Intel Xeon processor bus interface unit the hub interface unit and the DDR memory interface unit In addition the MCH incorporates a hub interface HI The HI interface allows the MCH to directly interface with the P64H2 The MCH also incr...

Page 24: ...P64 B supports two 184 pin 3 3 volt keyed 64 bit PCI expansion slot connectors running at 100MHz Both of the slots support 184 pin 3 3V keyed 64 bit PCI X expansion cards Both slots support full length PCI X or PCI add in cards The BIOS is responsible for setting the bus speed of P64 B The bus speed runs at the speed of the slowest card installed 3 2 3 2 PCI Bus P64 C I O Subsystem P64 C supports ...

Page 25: ...I Bus Master IDE Interface The ICH4 acts as a PCI based Ultra DMA 100 IDE controller that supports programmed I O transfers and bus master IDE transfers The ICH4 supports two IDE channels supporting two drives each drives 0 and 1 The baseboard provides two 40 pin 2x20 IDE connectors to access the IDE functionality The IDE interface supports Ultra DMA 100 Synchronous DMA Mode transfers on each 40 p...

Page 26: ...O R04h 0 always 1 GPIO R2Ch 0 1 Active Low PM R2Eh 0 1 Normal 0 SMI or SCI or Wakeup event GPI1 REQB Core BUS P2 ICH4 Parity DETECT P2_PERR GPI GPIO R00h 1 1 GPIO GPIO R04h 1 always 1 GPIO R2Ch 1 1 Active Low PM R2Eh 1 1 Normal 0 SMI or SCI or Wakeup Event GPI2 PIRQE Core PIRQ_E GPIO R00h 2 0 PIRQ_E GPI3 PIRQF Core PIRQ_F GPIO R00h 3 0 PIRQ_F GPI4 PIRQG Core PIRQ_G GPIO R00h 4 0 PIRQ_G GPI5 PIRQH ...

Page 27: ...ys 0 GPIO R0Ch 18 23 TTL Driver Output GPIO24 Resume N C GPO GPIO R04h 24 0 GPIO R0Ch 24 TTL Driver Output GPIO25 Resume CPU1 SKTOCC GPI GPIO R04h 25 1 GPIO R0Ch 25 0 Active Low GPIO R0Ch 25 GPIO26 N A GPIO27 Resume NC GPI GPIO R04h 27 1 GPIO R0Ch 27 0 Active Low GPIO R0Ch 27 GPIO28 Resume NC GPI GPIO R04h 28 1 GPIO R0Ch 28 0 Active Low GPIO R0Ch 28 GPIO29 31 N A GPIO32 USBLED_A Core NC GPI GPIO R...

Page 28: ...S_NIC1 GPO GPIO R30h 10 1b GPIO R34h 10 0b GPIO R38h 10 0 Disabled 1 Enabled GPIO43 USBLED_L Core NC GPO GPIO R30h 11 1b GPIO R34h 11 0b GPIO R38h 11 3 2 4 7 Power Management One of the embedded functions of the ICH4 is a power management controller This is used to implement ACPI compliant power management features The baseboard does support sleep states S0 S1 S4 and S5 3 3 Super I O The Winbond 8...

Page 29: ...al GPIO26 Pin 87 Btn_dsabl GPO CR2B 2 1 LD8 F0h 6 0 LD8 F1h 6 0 Power button Disabled 1 normal GPIO35 Pin 64 Blink_LED SUSLED CR29h 7 0 3 3 2 Serial Ports The board provides two serial ports an external serial port and an internal serial header The following sections provide details on the use of the serial ports 3 3 2 1 Serial A Serial A is a standard DB9 interface located at the rear I O panel o...

Page 30: ...of the baseboard are provided to access the keyboard or mouse functions The two ports are interchangeable and will automatically detect and configure a keyboard or mouse plugged into either port 3 3 2 5 Wake up Control The sIO contains functionality that allows various events to control the power on and power off the system 3 3 3 BIOS Flash The board incorporates an Intel N82802AC FWH8 flash memor...

Page 31: ...nd voltage levels as required including the following 100 MHz at 3 3 V logic levels For Processor 0 Processor 1 Debug Port and MCH 66 MHz at 3 3 V logic levels For MCH ICH4 AGP and P64H2 48 MHz at 3 3V logic levels For ICH4 33 MHz at 3 3V logic levels For ICH4 PCI Connector sIO and FWH 14 318 MHz at 2 5 V logic levels For ICH4 and sIO The following figure illustrates clock generation and distribut...

Page 32: ...Clock Generation and Distribution Intel Server Board SE7505VB2 Figure 4 SE7505VB2 Clock Distribution Diagram Revision 1 2 Intel part number C32194 002 32 ...

Page 33: ...s the P32 A segment The P32 A segment supports the following embedded devices and connectors Serial ATA controller Silicon Image 3112A One 10 100 Network Interface Controller Intel 82550PM Fast Ethernet Controller 2D 3D Graphics Accelerator ATI Rage XL Video Controller The Serial ATA controller and the NIC will each be allocated a GPIO to disable the device The video controller will be disabled wh...

Page 34: ... 64 bit bus segments are directed through the P64H2 I O Bridge The first PCI segment P64 B provides two 3 3V 64 bit PCI X slots capable of 100 MHz operation and support full length PCI cards The second PCI segment P64 C provides a single 3 3V 64 bit PCI slot operating at 66 MHz This segment supports full length PCI cards P64 C also has an embedded Intel 82540EM fast Ethernet gigabit controller 5 1...

Page 35: ...itration connections Table 13 P64 C Arbitration Connections Baseboard Signals Device P64_S_REQ0 P64_S_GNT0 PCI 66MHz Slot 5 P64_S_REQ1 P64_S_GNT1 Intel 82540EM Fast Ethenet Controller NIC 2 5 2 Serial ATA Controller The board provides an embedded dual port Serial ATA controller through the use of the Silicon Image 3112A ASIC The Silicon Image 3112A provides a single 32 bit 33 MHz PCI bus master in...

Page 36: ...est drive size 2 RAID 1 Mirroring Normal 50 min 2 RAID 0 configurations are primarily used for high performance applications as it doubles the sustained transfer rate of its drives RAID 1 configurations are primarily used for data protection RAID 1 creates an identical backup of the primary drive to a secondary drive Whenever a disk write is performed the controller sends data simultaneously to a ...

Page 37: ...60 72 75 90 100 Supported Supported Supported Supported 800x600 60 70 75 90 100 Supported Supported Supported Supported 1024x768 60 72 75 90 100 Supported Supported Supported Supported 1280x1024 43 60 70 72 Supported Supported 1600x1200 60 66 76 85 Supported 3D Mode Refresh Rate Hz SE7505VB2 3D Video Mode Support with Z Buffer Disabled 640x480 60 72 75 90 100 Supported Supported Supported Supporte...

Page 38: ...llowing diagram shows the signals for the PCI interface PCICLK CPUCLK AD 31 0 AD 31 0 C BE 3 0 C BE 3 0 PAR PAR FRAME FRAME IRDY IRDY IDSEL IDSEL PCIRST RESET TRDY TRDY STOP STOP INTR INTR DEVSEL DEVSEL REQ REQ GNT GNT PCI Bus Video Figure 5 Video Controller PCI Bus Interface Revision 1 2 Intel part number C32194 002 38 ...

Page 39: ...upport Low power 3 3 V device The 82540EM is a single compact component with integrated gigabit Ethernet MAC and PHY layer functions and is packaged in a 15mm2 TFBGA The baseboard supports independent disabling of the two NIC controllers using the BIOS setup menu The 82540EM supports the following features Support for the 33 66MHz bus segment Integrated 10 100 1000 Mb s full and half duplex operat...

Page 40: ... processors Table 16 PCI Interrupt Routing Sharing Interrupt INT A INT B INT C INT D AGPA ICH4_PIRQA AGPB ICH4_PIRQB VGA ICH4_PIRQB sATA ICH4_PIRQD NIC1 ICH4 PIRQC NIC2 P1 IRQ4 P64H2 A P1 P2 ICH4_PIRQE P64 C Slot 5 P1_IRQ0 P1_IRQ1 P1_IRQ2 P1_IRQ3 P64 B Slot 4 P2_IRQ0 P2_IRQ1 P2_IRQ2 P2_IRQ3 P64 B Slot 3 P2_IRQ4 P2_IRQ5 P2_IRQ6 P2_IRQ7 P32 A Slot 2 ICH4_PIRQG ICH4_PIRQF ICH4_PIRQE ICH4_PIRQH P32 A ...

Page 41: ...tor sourced by the ICH4 to the processors 5 5 3 Serialized IRQ Support The SE7505VB2 server board supports a serialized interrupt delivery mechanism Serialized Interrupt Requests SERIRQ consists of a start frame a minimum of 17 IRQ data channels and a stop frame Any slave device in the quiet mode may initiate the start frame While in the continuous mode the start frame is initiated by the host con...

Page 42: ...ACE ICH4 8259PIC IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IRQ16 IRQ17 IRQ18 IRQ19 IRQ20 IRQ21 IRQ22 IRQ23 CPU1 CPU2 INTR INTR HI1 5 INTERFACE IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IRQ16 IRQ17 IRQ18 IRQ19 IRQ20 IRQ21 IRQ22 IRQ23 P64H2 IOAPIC 2 P64H2 IOAPIC 1 Figure 6 Interrupt Routing Diagram ICH4 Internal ...

Page 43: ... ISA ISA Floppy ISA ISA RTC SCI ISA ISA ISA Mouse ISA Coprocessor Error P IDE ISA Not Used Cascade Serialized IRQ Interface SERIRQ AGPB VGA NIC1 AGPA sATA P64H2 A P1 P2 Slot 1 D Slot 2 C Slot 1 A Slot 2 B Slot 2 A Slot 1 B Slot 1 C Slot 2 D ICH4 Interrupt Routing SERIRQ Figure 7 Interrupt Routing Diagram Revision 1 2 Intel part number C32194 002 43 ...

Page 44: ... PIRQC ICH4 PIRQD P2 IRQ0 P2 IRQ1 P2 IRQ2 P2 IRQ3 P2 IRQ4 P2 IRQ5 P2 IRQ6 P2 IRQ7 P1 IRQ0 P1 IRQ1 P1 IRQ2 P1 IRQ3 P1 IRQ4 NIC2 AGPA NIC1 sATA AGPB VGA P64H2 A P1 P2 SLOT 5 SLOT 4 Note P1 is P64H2 PCI bus B P2 is P64H2 PCI bus C SLOT 3 SLOT 2 SLOT 1 Figure 8 The Board PCI Interrupt Mapping Diagram Revision 1 2 Intel part number C32194 002 44 ...

Page 45: ...ge sIO 1 8V Monitors 1 8V sIO 3 3V Monitors 3 3V sIO 5V Monitors 5VSB Internal sIO SB3V Monitors 12Vin sIO ENG12V Monitors 12Vin should be same as 12V Power Supply sIO 2 5V Monitors 5V sIO Vbat Monitors battery voltage sIO SB5V Monitors 5VSB sIO Fan Speed PWM1 Controls system fans sIO CPU fans invariable speed sIO TACH1 Monitors system fan 1 front sIO TACH2 Monitors system fan 2 front sIO TACH3 Mo...

Page 46: ...m Fan Limit 70 Rear System Fan Count Limit 6 2V 26h 1750 RPM 1222 RPM 8Ah 7 5V 27h 2300 RPM 1607 RPM 69h 10 5V 2Ah 3250 RPM 2250 RPM 4Bh 12 0V 2Fh 3700 RPM 2556 RPM 42h Voltage Duty Cycle Front System Fan NMB Front System Fan Limit 70 Front System Fan Count Limit 6 2V 26h 2650 RPM 1854 RPM 5Bh 7 5V 27h 3100 RPM 2163 RPM 4Eh 10 5V 2Ah 4000 RPM 2766 RPM 3Dh 12 0V 2Fh 4300 RPM 2960 RPM 39h CPU Fan Sp...

Page 47: ...e Sensor 3 High Byte Index 50h Bank 2 CPU2 VCOREA Index 20h Vcpu VCOREB Index 21h 1 8V V3 3 Index 22h 3 3V AVCC 5V 12VIN Index 24h SB3V 12VIN Index 25h ENG12V 5VIN Index 26h 2 5V PWM1 System fans J5K2 J5K3 J8A2 J5A2 PWM2 NC Vbat Battery 5VSB SB5V VTIN1 Ambient Temperature TACH1 Sys fan 1 J5K3 TACH2 Sys fan 2 J5K2 TACH6 CPU fan 1 J7B1 TACH5 CPU fan 2 J8A3 TACH4 Sys fan 3 J8A2 TACH3 Sys fan 4 J5A2 F...

Page 48: ...is enabled S1 Sleep State The S1 sleep state is a low wake up latency sleep state In this state no system context is lost Processor or chipset The system context is maintained by the hardware S4 Sleep State The S4 Non Volatile Sleep state NVS is a special global system state that allows system context to be saved and restored relatively slowly when power is lost to the baseboard If the system has ...

Page 49: ...Reset Button The reset button will generate a hard reset to the system NMI Button The NMI button will force an NMI to the processors 7 1 2 Wake up Sources ACPI and Legacy The baseboard is capable of wake up from several sources under a non ACPI configuration such as when the operating system does not support ACPI The wake up sources are defined in the following table Table 19 Supported Wake Events...

Page 50: ...e Black GND 15 3 GND Black Green DC_ON 16 4 5V Red Black GND 17 5 GND Black Black GND 18 6 5V Red Black GND 19 7 GND Black White 20 8 PS_GOOD Gray Red 5V 21 9 SB5V Purple Red 5V 22 10 12V Yellow Red 5V 23 11 12V Yellow Black GND 24 12 3 3V Orange Table 21 Auxiliary Signal Connector J7K1 Pin Signal Color 1 SCL Green 2 SDA Yellow 3 PWR_Alert Red 4 GNDsens Black 5 3 3Vsens Orange Table 22 Auxiliary C...

Page 51: ...167 NC 15 VDDQ 46 Pin Back A5 154 63 DQ45 DQ41 96 5 DM0 DQ2 129 38 A3 DQ26 161 70 DQ47 CS2 103 12 VDDQ DQ9 136 45 CK0 VDD 76 CK2 107 DM1 138 CK0 168 VDD 16 CK1 47 DQS8 VDDQ 108 VDD 139 VSS 169 DM6 17 48 A0 78 DQS6 109 DQ14 140 DM8 170 18 VSS 49 CB2 79 DQ50 110 DQ15 A10 171 DQ55 19 DQ10 50 VSS 80 111 CKE1 142 CB6 172 VDDQ 20 DQ11 CB3 81 VSS 112 VDDQ 143 VDDQ 173 NC 21 CKE0 52 BA1 82 VDDID 113 BA2 1...

Page 52: ... VSS AB16 D32 A15 Reserved E12 VCC K30 VSS U25 VCC AB17 D31 A16 Reserved E13 A28 K31 VCC U26 VSS AB18 VCC A17 LOCK E14 A24 L1 VSS U27 VCC AB19 D14 A18 VCC E15 VSS L2 VCC U28 VSS AB20 D12 A19 A7 E16 COMP1 L3 VSS U29 VCC AB21 VSS A20 A4 E17 VSS L4 VCC U30 VSS AB22 D13 A21 VSS E18 DRDY L5 VSS U31 VCC AB23 D9 A22 A3 E19 TRDY L6 VCC V1 VSS AB24 VCC A23 HITM E20 VCC L7 VSS V2 VCC AB25 D8 A24 VCC E21 RS0...

Page 53: ... SM_DAT B28 VSS F25 VSS N7 VCC Y2 VCC AC30 VSS B29 VCC F26 THERMTRIP N8 VSS Y3 Reserved AC31 VCC B30 VSS F27 A20M N9 VCC Y4 BCLK0 AD1 Reserved B31 VCC F28 VSS N23 VCC Y5 VSS AD2 VCC C1 VSS F29 VCC N24 VSS Y6 TESTHI3 AD3 VSS C2 VCC F30 VSS N25 VCC Y7 VSS AD4 VCCIOPLL C3 VID3 F31 VCC N26 VSS Y8 RESET AD5 TESTHI5 C4 VCC G1 VSS N27 VCC Y9 D62 AD6 VCC C5 Reserved G2 VCC N28 VSS Y10 VCC AD7 D57 C6 RSP G...

Page 54: ...AA19 D15 AE17 DP3 D15 A18 J7 VSS T2 VCC AA20 VCC AE18 VCC D16 A17 J8 VCC T3 VSS AA21 D11 AE19 DP1 D17 A9 J9 VSS T4 VCC AA22 D10 AE20 D28 D18 VCC J23 VSS T5 VSS AA23 VSS AE21 VSS D19 ADS J24 VCC T6 VCC AA24 D6 AE22 D27 D20 BR0 J25 VSS T7 VSS AA25 D3 AE23 D22 D21 VSS J26 VCC T8 VCC AA26 VCC AE24 VCC D22 RS1 J27 VSS T9 VSS AA27 D1 AE25 D19 D23 BPRI J28 VCC T23 VSS AA28 SM_TS1_A0 AE26 D16 D24 VCC J29 ...

Page 55: ...ound FRAME 4 TDO TDI 35 IRDY Ground 5 5V 5V 36 3 3V TRDY 6 5V INTA 37 DEVSEL Ground 7 INTB INTC 38 Ground STOP 8 INTD 5V 39 LOCK 3 3V 9 PRSNT1 Reserved 40 PERR SMBCLK 10 Reserved 5V I O 41 3 3V SMBDAT 11 PRSNT2 Reserved 42 SERR Ground 12 Ground Ground 43 3 3V PAR 13 Ground Ground 44 C BE 1 AD 15 14 Reserved 3 3Vaux 45 AD 14 3 3V 15 Ground RST 46 Ground AD 13 16 CLK 5V I O 47 AD 12 AD 11 17 Ground ...

Page 56: ...Q Ground 64 Ground C BE 7 19 3 3V I O PME 65 C BE 6 C BE 5 20 AD 31 AD 30 A 66 C BE 4 3 3V I O 21 AD 29 3 3V 67 Ground PAR64 22 Ground AD 28 68 AD 63 AD 62 23 AD 27 AD 26 69 AD 61 Ground 24 AD 25 Ground 70 3 3V I O AD 60 25 3 3V AD 24 71 AD 59 AD 58 26 C BE 3 IDSEL 72 AD 57 Ground 27 AD 23 3 3V 73 Ground AD 56 28 Ground AD 22 74 AD 55 AD 54 29 AD 21 AD 20 75 AD 53 3 3V I O 30 AD 19 Ground 76 Groun...

Page 57: ...EQ64 13 CONNECTOR KEY 61 5V 5V 14 Reserved 3 3Vaux 62 5V 5V 15 Ground RST CONNECTOR KEY 16 CLK 3 3V I O CONNECTOR KEY 17 Ground GNT 63 Reserved Ground 18 REQ Ground 64 Ground C BE 7 19 3 3V I O PME 65 C BE 6 C BE 5 20 AD 31 AD 30 A 66 C BE 4 3 3V I O 21 AD 29 3 3V 67 Ground PAR64 22 Ground AD 28 68 AD 63 AD 62 23 AD 27 AD 26 69 AD 61 Ground 24 AD 25 Ground 70 3 3V I O AD 60 25 3 3V AD 24 71 AD 59 ...

Page 58: ...B INTA 28 VCC3 3 VCC3 3 50 SERR PAR 7 CLK RST 29 AD27 AD26 51 C BE1 AD15 8 REQ GNT 30 AD25 AD24 52 Vddq1 5 Vddq1 5 9 VCC3 3 VCC3 3 31 GND GND 53 AD14 AD13 10 ST0 ST1 32 AD_STBF1 AD_STBS1 54 AD12 AD11 11 ST2 MB_DET 33 AD23 C BE3 55 GND GND 12 RBF DBI_HI 34 Vddq1 5 Vddq1 5 56 AD10 AD9 13 GND GND 35 AD21 AD22 57 AD8 C BE0 14 DBI_LO WBF 36 AD19 AD20 58 Vddq1 5 Vddq1 5 15 SBA0 SBA1 37 GND GND 59 AD_STB...

Page 59: ...FAULT LED ACPI switch 11 12 NIC2 ACT_LED ACPI switch GND 13 14 NIC2 ACT_LED RESET switch 15 16 SMB SDA RESET switch GND 17 18 SMB SCL Sleep switch 19 20 INDRUDER Sleep switch GND 21 22 NIC1 ACT_LED NMI switch 23 24 NIC1 ACT_LED Key 25 26 Key NC 27 28 NC NC 29 30 NC NC 31 32 NC NC 33 34 NC Note NC No Connect in this project 8 8 VGA Connector The following table details the pin out of the VGA connec...

Page 60: ...GIGA_MDI_3P 8 17 GND NIC_GIGA_MDI_3N 9 18 GND Table 33 NIC2 Gbit 10 100 1000 Connector Pin out J6A1 Signal Name Pin Pin Signal Name NIC_TXUP 1 8 GND GND 2 9 P3V_STAY NIC_TXUN 3 10 NIC_100_L NIC_RXIP 4 11 NIC_ACT_L GND 5 12 LK_STATUS2_L NIC_RXIN 6 13 GND NC 7 14 GND 8 10 IDE Connector The board provides two 40 pin ATA 100 IDE connectors Table 34 ATA 40 pin Connector Pin out J3K2 J4K1 Pin Signal Nam...

Page 61: ...ATA Connector Integrated on the baseboard is the Silicon Image 3112A dual port serial ATA controller with two serial ATA connectors The pin out for these two connectors is listed below Table 35 SATA Connector Pin out J1H1 Pin Signal Name 1 GND 2 S_TXP2N 3 S_TXN2N 4 GND 5 S_RXN2N 6 S_RXP2N 7 GND 8 GND 9 GND Table 36 SATA Connector Pin out J1H2 Pin Signal Name 1 GND 2 S_TXP1N 3 S_TXN1N 4 GND 5 S_RXN...

Page 62: ...line paired with DATAH1 7 DATAH1 Differential data line paired with DATAL1 8 GND 9 Fused VCC 5V w over current monitor of both port 0 and 1 10 DATAL2 Differential data line paired with DATAH2 11 DATAH2 Differential data line paired with DATAL2 12 GND 13 GND 14 GND 15 GND 16 GND A header on the server board provides an option to support one additional USB connector The pin out of the header is deta...

Page 63: ...TE GND 25 26 FDTRK0 Unused 27 28 FLWP GND 29 30 FRDATA GND 31 32 FHDSEL GND 33 34 FDSKCHG 8 14 Serial Port Connector Two serial ports are provided on the Server Board SE7505VB2 A standard external DB9 serial connector is located on the back edge of the baseboard to supply a Serial A interface A Serial B port is provided through a 9 pin header on the server board The following tables detail the pin...

Page 64: ...me 1 PS2_KBDATA_FB 2 TP_PS2_2 3 GND 4 PS2_KMPWR_FB 5 PS2_FBCLK_FB Keyboard 6 TP_PS2_6 7 PS2_MSEDATA_FB 8 TP_PS2_8 9 GND 10 PS2_KMPWR_RT 11 PS2_PSECLK_FB Mouse 12 TP_FS2_12 13 14 15 16 17 GND 8 16 Miscellaneous Headers 8 16 1 Fan Header There are six 3 pin fan headers All fans provide speed monitoring The fan headers are labeled CPU Fan 1 and 2 and SysFan 1 4 All fan headers have the same pin out a...

Page 65: ...Server Board SE7505VB2 SE7505VB2 Connectors 8 16 2 Intrusion Cable Connector Table 44 Intrusion Cable Connector Pin Out Pin Signal Name 1 Intruder_FET_L 2 P3V_STBY Revision 1 2 Intel part number C32194 002 65 ...

Page 66: ...d on pins 9 10 is used to perform different functions depending on the pins it is placed For normal operation this jumper should be on the storage pins 1 9 2 10 1 2 Clear Password 3 4 Recovery Mode 5 6 Clear CMOS 7 8 BIOS Boot Block Protect 9 10 Reserved Figure 10 System Recovery and Update Jumpers J4J1 The following table describes each jumper option Table 45 System Recovery and Update Jumper Opt...

Page 67: ... enabled In the two conditions listed above after rebooting you will see this prompt Press F2 to enter SETUP In a third condition when CMOS NVRAM has been corrupted you will see other prompts but not the F2 prompt Warning CMOS checksum invalid Warning CMOS time and date not set When this happens the BIOS will load default values for CMOS and attempt to boot 10 1 3 Setup Menus Each BIOS Setup menu ...

Page 68: ...pick list if a selected feature has a value field or to select a sub field for multi valued features like time and date If a pick list is displayed the Enter key will undo the pick list and allow another selection in the parent menu Esc Exit The ESC key provides a mechanism for backing out of any field This key will undo the pressing of the Enter key When the ESC key is pressed while editing any f...

Page 69: ...tions available in BIOS Setup Default settings are indicated in bold 10 1 4 Menu Selection Bar The Menu Selection Bar is located at the top of the screen and displays the major menu selections available to the user The menu bar is shown below Main Advanced Security Power Boot System Exit Table 48 lists the menus available in BIOS Setup Table 48 Menu Selection Bar Main Advanced Security Power Boot ...

Page 70: ... Choices Description System Time HH MM SS Sets the system time hour minutes and seconds on a 24 hour clock System Date MM DD YYYY Sets the system date month day year Legacy Diskette A Selects the diskette type Primary Master Select to display submenu Displays IDE device selection Primary Slave Select to display submenu Displays IDE device selection Secondary Master Select to display submenu Displa...

Page 71: ...Submenu Feature Choices Description Type No options Automatically detects the type of IDE device installed Multi Sector Transfers No options Specifies the number of sectors that are transferred per block during multiple sector transfers This option is disabled by default LBA Mode Control No options Enables Large Block Addressing LBA instead of cylinder head sector addressing This option is disable...

Page 72: ...Redirection Select to display submenu Provides additional options to configure the console Event Logging Select to display submenu Displays the event logs Hardware Monitor Select to display submenu Displays voltages temperatures and fan speeds for the system Installed O S Specifies the primary operating system An incorrect setting can cause some operating systems to behave erratically Note If you ...

Page 73: ...even if a mouse is not present Auto Detect will enable the PS 2 mouse only if one is present Summary Screen Enables or disables the boot time hardware BIOS summary screen Legacy USB Support Enables support for legacy USB It may be necessary to set this option to Disable to install NetWare 6 0 SP1 Hyper Threading Allows Intel Xeon processors to run in hyperthreading mode Enabling this setting will ...

Page 74: ...errupt This feature is present only when Serial Port B is set to Enabled Sets the interrupt for serial port B Parallel port Disabled Enables or disables the onboard parallel port Two devices cannot share the same IRQ Also choosing Disabled makes the parallel port unusable Mode This feature is present only when Parallel Port is set to Enabled Sets the mode for the parallel port Output only is the s...

Page 75: ...t 378 default 278 3BC IRQ 5 IRQ 7 default EPP option selected Interrupt Set the interrupt for parallel port IRQ 5 IRQ 7 default Note The Base I O address cannot be changed Its default value is set to 378 ECP option selected Base I O address Set the base I O address for parallel port Interrupt DMA Channel Set the DMA Channel for parallel port 378 default 278 3BC IRQ 5 IRQ 7 default Set the interrup...

Page 76: ... Serial ATA Enables the onboard serial ATA Onboard NIC 1 Enables the onboard PCI Intel 82550PM Controller Onboard NIC 2 Gbit Enables the onboard PCI Intel 82540EM Controller Onboard VGA Behavior Determines behavior of on board video If Single is selected then the onboard video controller will be disabled when an add in video card is detected If Dual is chosen then the onboard video controller will...

Page 77: ...Onboard Serial ATA Select to display submenu Enables the onboard Serial ATA See the Option ROM Scan Submenu Onboard NICs Select to display submenu Configures the onboard NICs See the Onboard NICs Submenu Slot 1 PCI 32 33 Select to display submenu Configures the specific PCI device expansion ROM See the Option ROM Scan Submenu Slot 2 PCI 32 33 Select to display submenu Configures the specific PCI d...

Page 78: ... NIC1 PXE Enabled support for onboard Intel 82550PM NIC PXE Note Once PXE boot is enabled it will not be selectable in the boot order until after a restart Onboard NIC2 Gbit PXE Enabled support for onboard Intel 82540EM NIC PXE Note Once PXE boot is enabled it will not be selectable in the boot order until after a restart Enabled Disabled default Enabled Disabled default Table 57 lists the options...

Page 79: ...tion Enables or disables nonmaskable interrupts NMI on parity errors on the PCI bus PERRs NMI on SERR Enables or disables NMI on system errors on the PCI bus SERRs NMI on PERR Disabled Enabled default Disabled Enabled default 10 1 6 5 Console Redirection Submenu To access this submenu select Advanced on the menu bar at the top of the screen and then Console Redirection Main Security Power Boot Sys...

Page 80: ...Console Type Enables the specified console type Flow Control None disallows flow control XON XOFF is software based asynchronous flow control CTS RTS is hardware based flow control When EMP is sharing the COM port as console redirection the flow control must be set to CTS RTS Console Connection Indicates whether the console is connected directly to the system or whether a modem is used Continue C ...

Page 81: ...idity No options Indicates if the contents of the event log are valid Event log capacity No options Indicates if there is space available in the event log View event log Enter Select Enter to display the current event log Only single bit error SBE and multi bit error MBE events on the memory bus are supported No Winbond W83627HF Super I 0 information is available Event Logging ECC Event Logging En...

Page 82: ...A No options Value fluctuates Example 1 45 V 1_8V_A No options Value fluctuates Example 1 79 V 3 3_V_A No options Value fluctuates Example 3 24 V AVCC No options Value fluctuates Example 5 02 V 3V_STBY_A No options Value fluctuates Example 3 28 V 12V_CPU_A No options Value fluctuates Example 11 12 V 2_5V_A No options Value fluctuates Example 2 49 V AUX5V No options Value fluctuates Example 4 94 V ...

Page 83: ...re prompted for a password press the ESC key to abort The supervisor password must be set if a user password is to be used NOTE Entering Setup with a supervisor password provides full access to all BIOS Setup utility menus Password on boot Requires password entry before boot System will remain in secure mode until password is entered If a user or supervisor password is not entered the operating sy...

Page 84: ...or off of the board Table 63 Power Menu Feature Choices Description Power Loss Control Specifies the power level the system returns to after AC power is lost Stay Off leaves the server power disabled and ACPI does not function to reboot the server in the event of a power failure Last State reboots the system according to ACPI standards Power Button Enables or disables the power button functionalit...

Page 85: ... st Boot Device 2nd Boot Device 3rd Boot Device 4th Boot Device Specifies the boot sequence according to the device type The computer will attempt to boot from up to four devices as specified here Only one of the devices can be an IDE hard disk drive The default settings for the first through fourth boot devices are respectively Removable Devices Hard Drive CD ROM Drive Removable Devices Attempts ...

Page 86: ... the processor Boot Strap Processor Application Processor Memory Enter Provides basic information on the memory Manufacturer Intel Corporation Product SE7505VB2 Version 1 00 Serial Number varies Installed Speed 2 8 GHz for example Socket Name BSP Manufacturer GenuineIntel Version Intel R XEON TM CPUID 3FEBFBFF00000F24 L2 Cache 512 KB Installed Speed 2 8 GHZ for example Socket Name AP Manufacturer ...

Page 87: ... Exit Table 66 lists the options available in the Exit menu Select an option using the up or down arrow keys then press Enter to execute the option Pressing Esc does not exit this menu You must select one of the items from the menu or menu bar to exit Table 66 Exit Menu Choices Description Exit Saving Changes Exits after writing all modified Setup item values to CMOS Exit Discarding Changes Exits ...

Page 88: ...ning the Upgrade Utility You can upgrade to a new version of the BIOS using the new BIOS files and the BIOS upgrade utility PHLASH16 EXE You can obtain the BIOS upgrade file and the PHLASH EXE utility from the Intel Customer Support Web site http support intel com support motherboards server SE7505VB2 Note Please review the instructions distributed with the upgrade utility before attempting a BIOS...

Page 89: ... steps above into the diskette drive 4 Copy the BIOS update files from the temporary folder onto the bootable diskette 10 2 2 Upgrading the BIOS Note Make sure to read your BIOS release notes for any specific instructions on updating the BIOS i e special jumper settings 1 Place the bootable diskette containing the BIOS update files into the diskette drive of your system Boot the system with the di...

Page 90: ...em reboots 7 Enter Setup by pressing the F2 key during boot Once in Setup press the F9 and Enter to set the parameters back to default values If you do not set the CMOS values back to defaults using the F9 key the system may function erratically 8 Re enter the values you wrote down at the beginning of this process or if you saved your Custom Defaults reload them by choosing from the Exit menu the ...

Page 91: ... three options Create MINIDOS Crisis Disk Installs the necessary recovery files onto the A drive Use this option if the diskette you are using is already formatted and bootable Create FULLDOS Crisis Disk Makes the floppy disk in A bootable and then installs the necessary recovery files Use this option if the diskette you are using is blank but not bootable Format the A Drive Diskette Formats the d...

Page 92: ...11 BIOS Recovery Jumper 3 Insert the Crisis Recovery Diskette into the A diskette drive 4 Plug the system into the AC power source and power it on 5 A blue screen will be displayed and the recovery process will automatically run The system will continue to beep throughout the recovery process The recovery process is complete when the beeping stops 6 Remove the diskette 7 Power down and unplug the ...

Page 93: ... Log Error Messages The event The Event Log Message Post Code Timer failed Channel 2 Timer Not Functional A0h CMOS Battery Failure CMOS Battery Failure 09h CMOS Checksum Error CMOS Checksum Error 09h Floppy failure Floppy Drive A Error 8Ch Keybord stuck key Keyboard not functional stuck key 52h Keyboard not functional Keyboard not functional 70h The keyboard controller failed Keyboard Controller n...

Page 94: ... respect to ground 0 3 V to Vdd 0 3V 2 3 3 V Supply Voltage with Respect to ground 0 3 V to 3 63 V 5 V Supply Voltage with Respect to ground 0 3 V to 5 5 V Notes 1 Chassis design must provide proper airflow to avoid exceeding the processor maximum case temperature 2 VDD means supply voltage for the device 11 1 Mean Time Between Failures MTBF Test Results This section provides results of MTBF testi...

Page 95: ... System Board 5 3 3 12 12 5 5 VSB 5 3 3 12 12 5 5 VSB Processor Vcore 2 177 22 160 00 18 46 16 67 Processor VRD Eff 80 35 44 20 32 00 NB Intel E7505 MCH 1 5V 0 6A 1 0 90 80 0 72 1 04 0 833 E7505 Vcore 1 475V 2 1A 1 3 10 65 2 01 1 41 0 92 2 5V 6 8 A 1 65 11 05 3 63 2 36 1 475 V VRD Eff 80 0 18 20 0 14 1 2 V VRD Eff 80 0 62 20 0 40 2 5 V VRD Eff 80 3 40 20 2 21 SB ICH4 Vcc 3 3 V 2 01 65 1 31 0 61 0 ...

Page 96: ...tion is based on the SSI EPS12V Entry Power Supply specification Revision 1 6 Table 71 The Board Power Supply Voltage Specification Parameter Min Nom Max Units Tolerance 3 3 V 3 20 V 3 30 3 46 V Vrms 5 3 5 V 4 80 V 5 00 5 25 V Vrms 5 4 12 V 11 52 V 12 00 12 6 V Vrms 5 4 12 V 11 40 12 20 13 08 Vrms 9 5 5 VSB 4 80 V 5 00 5 25 V Vrms 5 4 12 2 1 Power Timing This section discusses the timing requireme...

Page 97: ... the PSON signal with the AC input applied The ACOK signal is not being used to enable the turn on timing of the power supply Table 72 Voltage Timing Parameters Item Description Min Max Units Tvout_rise Output voltage rise time from each main output 5 70 msec Tvout_on All main outputs must be within regulation of each other within this time 50 msec T vout_off All main outputs must leave regulation...

Page 98: ...oltages stay within regulation after loss of AC 18 msec pwok_holdup Delay from loss of AC to de assertion of PWOK 17 msec Tpson_on_delay Delay from PSON active to output voltages within regulation limits 5 400 msec T pson_pwok Delay from PSON deactive to PWOK being de asserted 50 msec Tpwok_on Delay from output voltages within regulation limits to PWOK asserted at turn on 200 1000 msec T pwok_off ...

Page 99: ...bined error of peak overshoot set point regulation and undershoot voltage shall be less than or equal to 5 of the output voltage setting The transient response measurements shall be made with a load changing repetition rate of 50 Hz to 5 kHz The load slew rate shall not be greater than 0 2 A µs Table 74 Transient Load Requirements Output Step Load Size Starting Level Finishing Level Slew Rate 3 3 ...

Page 100: ...representative FCC ICES 003 Class A Emissions USA Canada Verification CISPR 22Class A Emissions International EN55022 Class A Emissions CENELEC Europe EN55024 1998 Immunity CENELEC Europe CE EMC Directive 89 336 EEC CENELEC Europe VCCI Class A Emissions Japan AS NZS 3548 Class A Emissions Australia New Zealand BSMI CNS13438 Class A Emissions Taiwan GOST R 29216 91 Class A Emissions Russia GOST R 5...

Page 101: ...e Swan Swedish TCO All plastic parts shall be marked with the ISO11469 requirements for recycling All wiring harnesses shall be sourced from a UL approved wiring harness manufacturer All Fans shall have the minimum certifications UL and TUV or VDE All external power connectors shall have current limiting devices that have UL and TUV or VDE certifications and shall be suitable rated for the applica...

Page 102: ...land s Ministry of Economic Development emission requirements 13 2 4 BSMI Taiwan The BSMI DOC Mark is silk screened on the component side of the server board and the following BSMI EMC warning is located on solder side of the server board 13 3 Replacing the Back up Battery The lithium battery on the server board powers the real time clock RTC for up to 10 years in the absence of power When the bat...

Page 103: ...ri som anbefalt av apparatfabrikanten Brukt batteri returneres apparatleverandøren VARNING Explosionsfara vid felaktigt batteribyte Använd samma batterityp eller en ekvivalent typ som rekommenderas av apparattillverkaren Kassera använt batteri enligt fabrikantens instruktion VAROITUS Paristo voi räjähtää jos se on virheellisesti asennettu Vaihda paristo ainoastaan laitevalmistajan suosittelemaan t...

Page 104: ...s Intel Server Board SE7505VB2 14 Mechanical Specifications The following figure shows the server board mechanical drawing Figure 14 Intel Server Board SE7505VB2 Mechanical Drawing Revision 1 2 Intel part number C32194 002 104 ...

Page 105: ...Intel Server Board SE7505VB2 Mechanical Specifications Figure 15 Board Photograph Reference Only Revision 1 2 Intel part number C32194 002 105 ...

Page 106: ...ked 128 bytes of memory which normally resides on the server board ICH4 I O Controller Hub 4 ECC Error Checking and Correction ECP Extended Capabilities Port EMP Emergency management port EPP Enhanced Parallel Port mode EPS External Product Specification FRU Field replaceable unit GB 1024 MB GPIO General purpose I O Hz Hertz 1 cycle second I2C Inter integrated circuit bus IA Intel architecture IER...

Page 107: ...cess Memory RISC Reduced instruction set computing ROM Read Only Memory SDRAM Synchronous Dynamic RAM SMI Server management interrupt SMI is the highest priority nonmaskable interrupt TBD To Be Determined UART Universal asynchronous receiver and transmitter USB Universal Serial Bus Word 16 bit quantity Revision 1 2 Intel part number C32194 002 107 ...

Page 108: ...troller Specifications Technical Reference Manual Rev 2 01 VRM 9 1 Specification I2C Bus Specification USB 2 0 Intel Server Board SE7505VB2 BIOS EPS2 SSI EEB 3 0 Windows Logo SDG 3 0 ACPI 1 0b SMBIOS 2 3 1 PC2001 only if WS cert AGP 3 0 Spec AGP Design Guide Rev 1 5 AGP Pro 1 1 Spec Rev 1 1a 2 This document is not available as a downloadble file please contact your Intel field representative to ob...

Reviews:

No comments

Brands by name

Popular brands

Load more brands