Intel® Server Board SE7505VB2
PCI I/O Subsystem
5.5.2.1
Legacy Interrupt Sources
The table below recommends the logical interrupt mapping of interrupt sources on the board.
The actual interrupt map is defined using configuration registers in the ICH4.
Table 17. Interrupt Definitions
ISA Interrupt
Description
INTR Processor
interrupt.
NMI
NMI to processor.
IRQ0 System
timer
IRQ1 Keyboard
interrupt.
IRQ2 Slave
PIC
IRQ3
Serial port 1 or 2 interrupt from SIO device, user-configurable.
IRQ4
Serial port 1 or 2 interrupt from SIO device, user-configurable.
IRQ5
Parallel Port / Generic
IRQ6 Floppy
disk.
IRQ7
Parallel Port / Generic
IRQ8_L
Active low RTC interrupt.
IRQ9 SCI*
IRQ10 Generic
IRQ11 Generic
IRQ12 Mouse
interrupt.
IRQ13 Floaty
processor.
IRQ14
Compatibility IDE interrupt from primary channel IDE devices 0 and 1.
IRQ15
Secondary IDE Cable
SMI*
System Management Interrupt. General purpose indicator sourced by the ICH4 to the processors.
5.5.3
Serialized IRQ Support
The SE7505VB2 server board supports a serialized interrupt delivery mechanism. Serialized
Interrupt Requests (SERIRQ) consists of a start frame, a minimum of 17 IRQ / data channels,
and a stop frame. Any slave device in the quiet mode may initiate the start frame. While in the
continuous mode, the start frame is initiated by the host controller.
5.5.4
IRQ Scan for PCIIRQ
The IRQ / data frame structure includes the ability to handle up to 32 sampling channels with
the standard implementation using the minimum 17 sampling channels. The board has an
external PCI interrupt serializer for PCIIRQ scan mechanism of ICH4 to support 16 PCIIRQs.
5.6 PCI Error Handling
The PCI bus defines two error pins, PERR# and SERR#, for reporting PCI parity errors and
system errors, respectively. In the case of PERR#, the PCI bus master has the option to retry
the offending transaction, or to report it using SERR#. All other PCI-related errors are reported
by SERR#. SERR# is routed to NMI if enabled by BIOS.
Revision 1.2
Intel part number C32194-002
41
