Intel SE7221BK1-E - Server Board - Mainboard Technical Manual Download

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Glossary

SE7221BK1-E Technical Product Specification

Term Definition

LPC

Low pin count

LSB

Least Significant Bit

MB 1024

MBE Multi-Bit

Error

Ms milliseconds

MSB

Most Significant Bit

MTBF

Mean Time Between Failures

Mux multiplexor

NIC

Network Interface Card

NMI Non-maskable

Interrupt

OEM

Original equipment manufacturer

Ohm

Unit of electrical resistance

PBGA

Pin Ball Grid Array

PERR Parity

Error

PIO Programmable

I/O

PMB

Private Management Bus

PMC

Platform Management Controller

PME

Power Management Event

PnP

Plug and Play

POST

Power-on Self Test

PWM Pulse-Width

Modulator

RAIDIOS

RAID I/O Steering

RAM

Random Access Memory

RI Ring

Indicate

RISC

Reduced instruction set computing

RMCP

Remote Management Control Protocol

ROM

Read Only Memory

RTC

Real Time Clock

SBE

Single-Bit Error

SCI

System Configuration Interrupt

SDR

Sensor Data Record

SDRAM

Synchronous Dynamic RAM

SEL

System event log

SERIRQ

Serialized Interrupt Requests

SERR System

Error

SM Server

Management

SMI

Server management interrupt. SMI is the highest priority nonmaskable interrupt

SMM

System Management Mode

SMS

System Management Software

SNMP

Simple Network Management Protocol

SPD

Serial Presence Detect

SSI

Server Standards Infrastructure

TPS

Technical Product Specification

UART

Universal asynchronous receiver and transmitter

Summary of Contents for SE7221BK1-E - Server Board - Mainboard

Page 1: ...Intel Server Board SE7221BK1 E Technical Product Specification Intel order number C91860 001 Revision 1 5 September 2005 Enterprise Platforms and Services Marketing ...

Page 2: ...ted supported CPU matrix January 2005 1 2 Added Diagnostic LED codes to error handling and reporting section February 2005 1 3 Modified Diagnostic LED section Correct supported CPU matrix May 2005 1 4 Added Adaptive Slot pinouts September 2005 1 5 Added supported video This product specification applies to the Intel Server Board SE7221BK1 E with BIOS identifier SE7221BK10 86B Changes to this speci...

Page 3: ...cool Intel s own chassis are designed and tested to meet the intended thermal requirements of these components when the fully integrated system is used together It is the responsibility of the system integrator that chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of airflow required for their specific applicati...

Page 4: ...Memory Architecture Overview 10 4 1 2 Graphics Memory Controller Hub GMCH 10 4 1 3 ICH6R 11 4 2 Super I O 13 4 2 1 Serial Ports 13 4 2 2 BIOS Flash 14 4 2 3 System Health Support 14 5 I O Subsystem 14 5 1 PCI Subsystem 14 5 1 1 P32 A 32 bit 33 MHz PCI Subsystem 14 5 1 2 P32 B 66 MHz PCI X Subsystem SE7221BK1LX sku only 15 5 1 3 P64 C 66 100 MHz PCI X Subsystem 16 5 1 4 PCI E x8 17 5 2 Video Contro...

Page 5: ...nector 34 7 9 USB Connector 35 7 10 Floppy Connector 35 7 11 Serial Port Connector 36 7 12 Keyboard and Mouse Connector 37 7 13 Miscellaneous Headers 37 7 13 1 Fan Header 37 7 13 2 Intrusion Cable Connector 38 7 13 3 HDD LED Header 38 7 13 4 Rolling BIOS selection header 38 8 Configuration Jumpers 39 8 1 System Recovery and Update Jumpers 39 9 BIOS Setup Utility 40 9 1 Localization 40 9 2 Console ...

Page 6: ... Checkpoints 67 Table 75 DIM Code Checkpoints 68 Table 76 ACPI Runtime Checkpoints 68 9 8 Diagnostic LEDs 69 9 8 1 Diagnostic LED POST Progress Codes 69 Table 78 Boot Block POST Progress Codes 69 Table 79 POST Progress Codes 70 10 Power Information 73 10 1 Intel Server Board SE7221BK1 E Power Budget 73 10 2 Power Supply Specifications 74 10 2 1 Power Timing Requirements 74 10 2 2 Dynamic Loading 7...

Page 7: ...tromagnetic Compatibility Notices 83 13 2 1 FCC USA 83 13 2 2 INDUSTRY CANADA ICES 003 84 13 2 3 Europe CE Declaration of Conformity 84 13 2 4 Taiwan Declaration of Conformity 84 13 2 5 Korean RRL Compliance 84 13 2 6 Australia New Zealand 85 13 3 Replacing the Back Up Battery 85 13 4 Calculated Mean Time Between Failures MTBF 86 13 5 Mechanical Specifications 86 Glossary I ...

Page 8: ... Routing Sharing 18 Table 15 Interrupt Definitions 19 Table 16 Supported Wake Events 25 Table 17 Power Connector Pin out CN4H1 26 Table 18 Auxiliary CPU Power Connector Pin out CN4B1 26 Table 19 Intel Adaptive Slot pinout 27 Table 20 HSBP Header Pin out J1D1 30 Table 21 LCD Header Pin out J1C1 31 Table 22 LEGEND SE_LINK Header Pin out J2B1 31 Table 23 Front Panel 34 Pin Header Pin out J1J1 31 Tabl...

Page 9: ... USB Configuration Sub menu Selections 46 Table 50 BIOS Setup USB Mass Storage Device Configuration Sub menu Selections 47 Table 51 BIOS Setup PCI Configuration Sub menu Selections 47 Table 52 BIOS Setup Memory Configuration Sub menu Selections 48 Table 53 BIOS Setup Boot Menu Selections 49 Table 54 BIOS Setup Boot Settings Configuration Sub menu Selections 49 Table 55 BIOS Setup Boot Device Prior...

Page 10: ...ble 76 ACPI Runtime Checkpoints 68 Table 77 POST Progress Code LED Example 69 Table 78 Boot Block POST Progress Codes 69 Table 79 POST Progress Codes 70 Table 80 The Board Power Budget 73 Table 81 The Board Power Supply Voltage Specification 74 Table 82 Output Voltage Timing 74 Table 83 Turn On Off Timing 75 Table 84 Transient Load Requirements 76 Table 85 AC Line Sag Transient Performance 77 Tabl...

Page 11: ...ure 5 PXH Interrupt Routing Diagram 23 Figure 6 System Recovery and Update Jumpers J1F2 39 Figure 7 BIOS Recovery Jumper 62 Figure 8 Output Voltage Timing 75 Figure 9 Turn On Off Timing Power Supply Signals 76 Figure 10 Fan Speed Control Block Diagram 81 Figure 11 SE7221BK1 E Server Board Mechanical Drawing 87 Figure 12 SKU 1 Pedestal mount I O shield mechanical drawing 88 Figure 13 SKU 2 Pedestal...

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Page 13: ...tems that make up the server board This document is divided into the following main categories Chapter 2 Server Board Overview Chapter 3 Functional Architecture Chapter 4 The Intel E7221 Chipset Chapter 5 I O Subsystem Chapter 6 ACPI Implementation Chapter 7 Connectors Chapter 8 Configuration Jumpers Chapter 9 BIOS Setup Utility Chapter 10 Absolute Maximum Ratings Chapter 11 Power Information Chap...

Page 14: ... 4GB max memory capacity Support for 256MB 512MB 1GB and 2GB DRAM sizes Supports Performance Acceleration Technology PAT I O Subsystem Four independent PCI Buses Segment A One PCI 32 bit 33 MHz 5 V connector supporting full length PCI add in cards and one embedded device Supports PCI Specification Rev 2 3 One Intel 10 100 1000 82541PI gigabit Ethernet Controller Segment B One PCI 32 bit 66 MHz emb...

Page 15: ... S4 Supports legacy Keyboard Mouse connections when using PS2 USB dongle LPC Low Pin Count bus segment with one embedded devices Super I O Super IO controller chip NS PC87427 providing all PC compatible I O floppy serial keyboard mouse two serial com port and integrated hardware monitoring SSI compliant connectors for SSI interface support front panel and power connectors Support for up to four sy...

Page 16: ...o right DIMM 1A DIMM 2A X Serial ATA SATA 2 Connector C PCI X 100 SLOT N Front USB Header optional Y SATA 1 Connector D PCI X 100 SLOT O System Fan Headers for Intel Server Board SR1425BK1 E Z BIOS Control Jumper E PCI Express or Riser Connector Slot P System Fan 4 AA BIOS Select Jumper F 12v CPU Power Q System Fan 3 optional BB HDD LED Header G System Fan 1 optional R Main Power Connector CC HSBP...

Page 17: ...systems The Intel Celeron Processor currently does not support EM64T 3 1 1 Processor VRD The Intel Server Board SE7221BK1 E has a VRD Voltage Regulator Down to support one processor It is compliant with the VRM 10 1 DC DC Converter Design Guide Line and provides a maximum of 120A which is capable of supporting the requirements for Intel Pentium 4 and Intel Celeron D processors The board hardware m...

Page 18: ...d supports up to four DIMM slots for a maximum memory capacity of 4 GB The DIMM organization is x72 which includes eight ECC check bits The memory interface runs at 400 533MT s The memory controller supports memory scrubbing single bit error correction and multiple bit error detection and Intel x4 SDDC support with x4 DIMMs Memory can be implemented with either single sided one row or double sided...

Page 19: ...d DIMM_2B The sockets associated with each bank or channel are located next to each other and the DIMM socket identifiers are marked on the baseboard silkscreen near the DIMM socket Bank 1 is associated with Memory Channel A while Bank 2 is associated with Memory Channel B When only two DIMM modules are being used the population order must be DIMM_1A DIMM_1B to ensure dual channel operating mode T...

Page 20: ...ation Order J8J1 DIMM_1A A 1 J8J2 DIMM_2A A 3 J9J2 DIMM_1B B 2 J9J1 DIMM_2B B 4 1 3 2 4 Channel A Bank 1 Channel B Bank 2 DIMM_1A DIMM_2A DIMM_1B DIMM_2B J8J1 J8J2 J9J2 J9J1 Figure 2 Memory Bank Label Definition Table 3 summarizes the characteristics of dual and single channel configurations with and without the use of Dynamic Mode ...

Page 21: ...nd from memory The Intel E7221 GMCH comes with an integrated high performance graphics media accelerator Intel GMA 900 and supports one x8 port configuration PCI E interface Maximum theoretical peak bandwidth on each x8 PCI Express interface of 2 5 GB s in each direction simultaneously for 5 GB s per port ICH6R I O Controller Hub 6R The ICH6R controller has several components It provides the inter...

Page 22: ...ndustry standard DDR2 The following table shows the DDR2 DIMM technology supported Table 4 Supported DDR2 modules DDR2 400 and DDR2 533 Un buffered SDRAM Module Matrix DIMM Capacity DIMM Organization SDRAM Density SDRAM Organization SDRAM Devices rows Banks Address bits rows Banks column 256MB 32M x 72 256Mbit 32M x 8 9 1 4 13 2 10 512MB 64M x 72 256Mbit 32M x 8 18 2 4 13 2 10 512MB 64M x 72 512Mb...

Page 23: ...ICH6R has its own set of configuration registers Once configured each appears to the system as a distinct hardware controller sharing the same PCI bus interface The primary role of the ICH6R is to provide the gateway to all PC compatible I O devices and features The board uses the following the ICH6R features PCI 32 bit 33MHz interface LPC bus interface PCI Express x4 DMI Direct Media Interface ID...

Page 24: ...n main memory and up to four USB connectors All ports function identically and with the same bandwidth The Intel Server Board SE7221BK1 E implements four ports on the board The baseboard provides two external USB ports on the back of the server board The dual stack USB connector is located within the standard ATX I O panel area The Universal Serial Bus Specification Revision 1 1 defines the extern...

Page 25: ...or is J8A1 4 2 1 2 Serial B Serial B is an optional port accessed through a 9 pin internal header J1B1 A standard DH 10 to DB9 cable can be used to direct serial B to an external connector on any given chassis The serial B interface follows the standard RS232 pin out The baseboard has a Serial_B silkscreen label next to the connector and is located beside the PCI32 5V connector 4 2 1 3 Floppy Disk...

Page 26: ... 2 3 The P32 A bus segment is directed through the ICH6R The P32 B and P64 C bus segment are independently configured to PXH that is through ICH6R by PCI Express x 4 interface The PCI E x8 bus is directed through the GMCH The table below lists the characteristics of the three PCI bus segments Table 5 PCI Bus Segment Characteristics PCI Bus Segment Voltage Width Speed Type PCI I O Card Slots PCI 5V...

Page 27: ...1_N GNT_N1 Intel 82541PI LAN NIC1 PCI REQ0_N GNT_N0 PCI Slot 1 32bit 33MHz 5 1 2 P32 B 66 MHz PCI X Subsystem SE7221BK1LX sku only One 32 bit PCI bus segment is directed through the PXH interface A This PCI segment P32 B just has an embedded device Intel 82541PI LAN NIC2 clocked at 66MHz SE7221BK1LX sku only 5 1 2 1 Device IDs IDSEL Each device under the PCI hub bridge has its IDSEL signal connect...

Page 28: ...31 16 which acts as a chip select on the PCI bus segment in configuration cycles This determines a unique PCI device ID value for use in configuration cycles The following table shows the bit to which each IDSEL signal is attached for P64 C devices and corresponding device description Table 10 P64 C Configuration IDs IDSEL Value Device 17 PCI Slot 4 64bit 66 100MHz PCI Slot 6 64bit 100MHz Riser SE...

Page 29: ...stalled onboard system resources such as video consume a considerable amount of memory leaving just above 3 GB of available memory for the operating system Details of this issue have been communicated via the Technical Advisory TA_719 01 which can be found at http support intel com support motherboards server SE7221BK1 E The baseboard provides a standard 15 pin VGA connector at the rear of the sys...

Page 30: ...een LED indicates 100 Mbps operation when lit and 10 Mbps when off 5 4 Interrupt Routing The board interrupt architecture accommodates both PC compatible PIC mode and APIC mode interrupts through use of the integrated I O APICs in the ICH6 5 4 1 Legacy Interrupt Routing For PC compatible mode the ICH6 provides two 82C59 compatible interrupt controllers The two controllers are cascaded with interru...

Page 31: ...ap is defined using configuration registers in the ICH6 Table 15 Interrupt Definitions ISA Interrupt Description INTR Processor interrupt NMI NMI to processor IRQ0 System timer IRQ1 Keyboard interrupt IRQ2 Slave PIC IRQ3 Serial port 1 or 2 interrupt from SUPER IO device user configurable IRQ4 Serial port 1 or 2 interrupt from SUPER IO device user configurable IRQ5 IRQ6 Floppy disk IRQ7 Parallel Po...

Page 32: ... error pins PERR and SERR for reporting PCI parity errors and system errors respectively In the case of PERR the PCI bus master has the option to retry the offending transaction or to report it using SERR All other PCI related errors are reported by SERR SERR is routed to NMI if enabled by BIOS ...

Page 33: ... 3 Interrupt Routing Diagram IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IRQ16 IRQ17 IRQ18 IRQ19 IRQ20 IRQ21 IRQ22 IRQ23 ICH6 IOAPIC 0 ICH6 GMCH X8 PCI E interface ICH6 8259PIC X8 connector CPU INTR DMI INTERFACE ...

Page 34: ...QG PIRQH PIRQA Super I O Timer Keyboard Serial Port2 ISA Serial Port1 ISA ISA Floppy ISA ISA RTC SCI ISA ISA ISA Mouse ISA Coprocessor Error P IDE ISA Not Used Cascade Serialized IRQ Interface SERIRQ INTEL 82541PI NIC1 Slot 1 INTB SERIRQ ICH6 Interrupt Routing PCI Interface N A N A N A Slot 1 INTC Slot 1 INTA Slot 1 INTD ...

Page 35: ...B IRQ0 PB IRQ1 PB IRQ2 PB IRQ3 PB IRQ4 PB IRQ5 PB IRQ6 PB IRQ7 PB IRQ8 PB IRQ9 PB IRQ10 PB IRQ11 PB IRQ12 PB IRQ13 PB IRQ14 PB IRQ15 PXH PCI X Interface PCI X Interface N A N A N A INTEL 82541PI NIC2 N A N A N A N A N A N A N A N A N A N A N A N A Slot 4 INTA Slot 6 INTA Slot 4 INTB Slot 6 INTB Slot 4 INTC Slot 6 INTC Slot 4 INTD Slot 6 INTD Slot 5 INTD Slot 5 INTA Slot 5 INTB Slot 5 INTC N A N A ...

Page 36: ...ntained by the hardware S4 Sleep State The S4 Non Volatile Sleep state NVS is a special global system state that allows system context to be saved and restored relatively slowly when power is lost to the baseboard If the system has been commanded to enter the S4 sleep state the operating system will write the system context to a non volatile storage file and leave appropriate context markers S5 Sl...

Page 37: ...s capable of wake up from several sources under a non ACPI configuration such as when the operating system does not support ACPI The wake up sources are defined in the following table Table 16 Supported Wake Events Wake Event Supported via ACPI by sleep state Supported Via Legacy Wake Power Button Always wakes system Always wakes system PME from PCI 32 33 S1 S4 S5 PME from primary PCI 64 66 S1 S4 ...

Page 38: ...C Blue 2 3 3VDC Orange 15 COM Black 3 COM Black 16 PSON Green COM RS Black 24AWG 17 COM Black 4 5VDC Red 18 COM Black 5V RS Red 24AWG 19 COM Black 5 COM Black 20 Reserved N C 6 5VDC Red 21 5VDC Red 7 COM Black 22 5VDC Red 8 PWR OK Gray 23 5VDC Red 9 5 VSB Purple 24 COM Black 10 12V3 Yellow 11 12V3 Yellow 12 3 3VDC Orange Table 18 Auxiliary CPU Power Connector Pin out CN4B1 Pin Signal 18 AWG color ...

Page 39: ...x 10 3 3V 11 Wake 11 PERST KEY KEY KEY KEY KEY KEY KEY KEY 12 RSVD 12 GND 13 GND 13 REFCLK1 14 HSOp 0 14 REFCLK1 15 HSOn 0 15 GND 16 GND 16 HSIp 0 17 Present2 17 HSIn 0 18 GND 1X end 18 GND 19 HSOp 1 19 RSVD 20 HSOn 1 20 GND 21 GND 21 HSIp 1 22 GND 22 HSIn 1 23 HSOp 2 23 GND 24 HSOn 2 24 GND 25 GND 25 HSIp 2 26 GND 26 HSIn 2 27 HSOp 3 27 GND 28 HSOn 3 28 GND 29 GND 29 HSIp 3 30 RSVD 30 HSIn 3 31 P...

Page 40: ... board KEY KEY and allows a x8 to be used instead KEY KEY Blocks a x16 PCI Express board KEY KEY 50 12V 50 12V 51 5V 51 INTB 52 INTD 52 5V 53 5V 53 5V 54 5V 54 5V 55 INTA 55 INTC 56 GND 56 GND 57 CLK3 57 REQ3 58 GND 58 GND 59 CLK2 59 GNT3 60 GND 60 GND 61 REQ2 61 RST 62 GND 62 5V 63 GND 63 RSVD 64 CLK1 64 GND 65 GND 65 GNT2 66 REQ1 66 3 3V 67 3 3V 67 GNT1 68 PME2 68 GND 69 AD 31 69 PME1 70 AD 29 7...

Page 41: ... 90 3 3V 91 3 3V 91 SERR 92 C BE 1 92 GND 93 AD 14 93 PAR 94 GND 94 AD 15 95 AD 12 95 3 3V 96 AD 10 96 AD 13 97 M66EN 97 AD 11 98 GND 98 GND 99 GND 99 AD 09 100 AD 08 100 C BE 0 101 AD 07 101 3 3V 102 3 3V 102 AD 06 103 AD 05 103 AD 04 104 AD 03 104 GND 105 GND 105 AD 02 106 AD 01 106 AD 00 107 3 3V 107 3 3V 108 ACK64 108 REQ64 109 5V 109 5V 110 5V 110 5V 111 GND 111 C BE 7 112 C BE 6 112 C BE 5 1...

Page 42: ...D 129 AD 44 130 AD 43 130 AD 42 131 AD 41 131 3 3V 132 GND 132 AD 40 133 AD 39 133 AD 38 134 AD 37 134 GND 135 3 3V 135 AD 36 136 AD 35 136 AD 34 137 AD 33 137 GND 138 GND 138 AD 32 139 Type 1 0 139 1U 00 PCI Express 1U 01 PCI 1U 10 N A Type1 1U 11 N A GND 140 2U 00 2xPCI Express PCI 140 2U 01 3x PCI 2U 10 PXH 3 PCI X Type0 2U 11 No Riser Size 0 1U 1 2U Special Riser Signals 7 3 I2 C Header Table ...

Page 43: ...P5V_STBY POWER 5 POST_STATUS_N 6 FP_RST_BTN_N 7 P5V 8 FP_PWR_BTN_N 7 4 Front Panel Connector A standard SSI 34 pin header is provided to support a system front panel The header contains reset NMI power control buttons and LED indicators The following table details the pin out of this header Table 23 Front Panel 34 Pin Header Pin out J1J1 Signal Name Pin Pin Signal Name P5V_STB 1 2 P5V_STB KEY 3 4 ...

Page 44: ...fication 32 Signal Name Pin Pin Signal Name GND 21 22 LAN2_ACT_N NMI switch 23 24 LAN2_LINK_UP_N Key 25 26 Key P5V_STB 27 28 P5V_STB FP_ID_LED_N 29 30 FP_STATUS_LED1_N FP_ID_BTN_N 31 32 P5V GND 33 34 NC Note NC No Connect in this project ...

Page 45: ...llowing tables detail the pin out of the connector Table 25 NIC1 82541PI 10 100 1000 Connector Pin out J5A1 Signal Name Pin Pin Signal Name LGND_LAN1 1 10 LAN1_TRDN3 LAN1_TRDP0 2 11 LAN1_LINK_UP_N LAN1_TRDN0 3 12 LAN1_ACT_N LAN1_TRDP1 4 LAN1_TRDP3 9 LAN1_TRDN1 5 13 LAN1_LINK100_N P1V8_STB_LAN1 6 14 P3V3_STB LAN1_TRDP2 7 15 LAN1_LINK1000_N LAN1_TRDN2 8 16 LINK100_L Table 26 NIC2 82541PI 10 100 1000...

Page 46: ..._DD12 13 IDE_DD2 14 IDE_DD13 15 IDE_DD1 16 IDE_DD14 17 IDE_DD0 18 IDE_DD15 19 GND 20 KEY 21 IDE_DMAREQ 22 GND 23 IDE_IOW 24 GND 25 IDE_IOR 26 GND 27 IDE_IORDY 28 GND 29 IDE_DMAACK 30 GND 31 IRQ_IDE 32 Test Point 33 IDE_A1 34 DIAG 35 IDE_A0 36 IDE_A2 37 IDE_DCS0 38 IDE_DCS1 39 IDE_HD_ACT 40 GND 7 8 SATA Connector ICH6R integrated a SATA controller with four SATA ports output The pin out for these f...

Page 47: ... is detailed in the following table Table 30 Optional USB Connection Header Pin out J4F1 Signal Name Pin Pin Signal Name Fused VCC 5V w over current monitor of both port 1 1 2 Fused VCC 5V w over current monitor of both port 0 USB_B2_N 3 4 USB_B1_N USB_B2_P 5 6 USB_B1_P GND 7 8 GND Key 9 10 NC 7 10 Floppy Connector The board provides a standard 34 pin interface to the floppy drive controller The f...

Page 48: ... connector is located on the back edge of the baseboard to supply a Serial A interface This connector is combined with VGA connector J8A1 A Serial B port is provided through a 9 pin header J1B1 on the server board The following tables detail the pin outs of these two ports Table 32 External DB9 Serial A Port Pin out J8A1 Signal Name Pin Pin Signal Name DCD P T1 T6 DSR P RXD P T2 T7 RTS P TXD P T3 ...

Page 49: ... fan headers have the same pin out and are detailed below Table 35 Three pin Fan Headers Pin out JP5J1 JP5J2 JP7A1 JP6A1 Pin Signal Name Type Description 1 Ground Power GROUND is the power supply ground 2 Fan Power Power Fan Power with FAN_SPEED_CNTL1 Fan speed control 3 Fan Tach Out FAN_TACH signal is connected to the LM96000 to monitor the FAN speed There are also four 8 pin fan headers J6J1 J6J...

Page 50: ...or HDD LED Connection This jumper reserves for PCI add in card which supports the SCSI or SATA interface with external HDD LED activity cable Table 38 HDD LED Header J1E1 Pin Out Pin Signal Name 1 HDD_LED_ACT_N 2 NC 7 13 4 Rolling BIOS selection header There is a 1x3 pin Header that is used to configure the function of rolling BIOS The figure below shows the jumper pins and their functions The fac...

Page 51: ...e set to a protected mode for each function Three jumpers are stored on six pins during normal operation Please refer to below figure for the detail function Figure 6 System Recovery and Update Jumpers J1F2 The following table describes each jumper option Table 40 System Recovery and Update Jumper Options Function Pin Pin Function Description 1 2 MBMC control CMOS CLEAR 2 3 Force erase 5 6 Protect...

Page 52: ...lation This may limit some functionality for compatibility e g usage of colors or some keys or key sequences or support of pointing devices 9 3 Configuration Reset There are different mechanisms for resetting the system configuration to default values When a reset system configuration request is detected the BIOS will load the default system configuration values during the next POST A reset system...

Page 53: ...ffect if a sub menu or pick list is displayed Tab Select Field The Tab key is used to move between fields For example Tab can be used to move from hours to minutes in the time item in the main menu Change Value The minus key on the keypad is used to change the value of the current item to the previous value This key scrolls through the values in the associated pick list without displaying the full...

Page 54: ... The following tables describe the available options on the top level and lower level menus Default values are shown in bold text Table 42 BIOS Setup Main Menu Options Feature Options Help Text Description System Overview N A N A AMIBIOS N A N A Version N A N A BIOS ID string excluding the build time and date Build Date MM DD YY N A BIOS build date Processor N A N A Type N A N A Processor brand ID...

Page 55: ... Selects submenu 9 5 2 1 Processor configuration sub menu Table 44 BIOS Setup Processor configuration sub menu options Feature Options Help Text Description Manufacturer Intel N A Displays processor manufacturer string Brand String N A N A Displays processor brand ID string Frequency N A N A Displays the calculated processor speed FSB Speed N A N A Displays the processor front side bus speed Cache...

Page 56: ... SATA controller enabled only PATA Pri SATA Sec PATA controller is primary SATA is secondary SATA Pri PATA Sec SATA controller is primary PATA is secondary PATA Only PATA controller enabled only This option will be hided when ATA IDE configuration Disabled In compatible mode this item will be used Configure S ATA as IDE RAID AHCI In Enhance mode this item will be showed Stagger Spinup support Disa...

Page 57: ...s IDE Detect Time Out Sec 0 5 10 15 20 25 30 35 Select the time out value for detecting ATA ATAPI device s Primarily used with older IDE devices with longer spin up times ATA PI 80Pin Cable Detection Host Device Host Device Select the mechanism for detecting 80Pin ATA PI Cable Table 46 BIOS Setup IDE Device Configuration Sub menu Selections Feature Options Help Text Description Device N A N A Disp...

Page 58: ...Self Monitoring Analysis and Reporting Technology The Auto setting should work in most cases 32Bit Data Transfer Disabled Enabled Enable Disable 32 bit Data Transfer 9 5 2 3 Floppy configuration sub menu Table 47 BIOS Setup Floppy Configuration Sub menu Selections Feature Options Help Text Description Floppy A Disabled 1 44 MB 3 1 2 Select the type of floppy drive connected to the system Note Inte...

Page 59: ...ices are connected Port 64 60 Emulation Disabled Enabled Enables I O port 60 64h emulation support This should be enabled for the complete USB keyboard legacy support for non USB aware OS USB 2 0 Controller Enabled Disabled N A USB 2 0 Controller mode FullSpeed HiSpeed Configures the USB 2 0 controller in HiSpeed 480 Mbps or FullSpeed 12 Mbps When USB 2 0 Controller is disabled it will disappear U...

Page 60: ... to force a HDD formatted drive to boot as FDD Ex ZIP drive 9 5 2 6 PCI configuration sub menu This sub menu provides control over PCI devices and their option ROM s If the BIOS is reporting POST error 146 use this menu to disable option ROM s that are not required to boot the system Table 51 BIOS Setup PCI Configuration Sub menu Selections Feature Options Help Text Description Onboard Video Disab...

Page 61: ...tended memory test Memory Retest Enabled Disabled If Enabled BIOS will activate and retest all DIMM s on the next system boot This option will automactically reset to Disabled on the next system boot 9 5 3 Boot menu Table 53 BIOS Setup Boot Menu Selections Feature Options Help Text Description Boot Settings Configuration N A Configure settings during system boot Selects submenu Boot Device Priorit...

Page 62: ...lays Press F2 to run Setup in POST Scan User Flash Area Disabled Enabled Allows BIOS to scan the Flash ROM for user binaries 9 5 3 2 Boot device priority sub menu selections Table 55 BIOS Setup Boot Device Priority Sub menu Selections Feature Options Help Text Description 1st Boot Device Varies Specifies the boot sequence from the available devices A device enclosed in parenthesis has been disable...

Page 63: ...es the boot sequence from the available devices Varies based on system configuration 9 5 4 Chipset Menu Table 59 BIOS Setup ATAPI CDROM Drives Sub menu Selections Feature Options Help Text Description North Bridge Configuration N A Configure North Bridge features Opens sub screen to configure NB South Bridge Configuration N A Configure South bridge features Opens sub screen to configure SB Intel P...

Page 64: ...rge 4 DRAM Clocks 5 DRAM Clocks 6 DRAM Clocks 7 DRAM Clocks 8 DRAM Clocks 9 DRAM Clocks 10 DRAM Clocks 11 DRAM Clocks 12 DRAM Clocks 13 DRAM Clocks 14 DRAM Clocks 15 DRAM Clocks Select RAS Activate to precharge Greyed when DRAM timing programming are done using SPD RAS activate to precharge setting will be programmed into DRAM timing register when manual setting is selected Boots Grapchics Adapter...

Page 65: ...r handling Clear Errors Leave Errors Select the method of handling for sticky RAS errors RAS errors handing method selection VGA 16 Bit decode Disabled Enabled Enabled Disable decoding of VGA for devices behind PXH 9 5 5 Security menu Table 63 BIOS Setup Security Menu Options Feature Options Help Text Description Administrator Password is N A Install Not installed Informational display User Passwo...

Page 66: ... is enabled Can be disabled by entering a new key followed by a backspace or by entering delete This node is grayed out if a password is not installed Secure Mode Boot Disabled Enabled When enabled allows the host system to complete the boot process without a password The keyboard will remain locked until a password is entered A password is required to boot from diskette This node is grayed out if...

Page 67: ...inutes 20 minutes This controls the time limit allowed for booting an operating system using PXE boot The action taken on timeout is determined by OS Watchdog Timer policy setting OS Watchdog Timer Policy Stay On Reset Power Off Controls the policy upon timeout Stay on action will take no overt action Reset will force the system to reset Power off will force the system to power off Platform Event ...

Page 68: ...XON XOFF Software CTS RTS CD Hardware Carrier Detect for modem use Terminal Type PC ANSI VT100 VT UTF8 VT100 selection only works for English as the selected language VT UTF8 uses Unicode PC ANSI is the standard PC type terminal 9 5 6 3 Event Log configuration sub menu selections Table 67 BIOS Setup Event Log Configuration Sub menu Selections Feature Options Help Text Description Clear All Event L...

Page 69: ...so far to any of the setup questions F7 key can be used for this operation Load Setup Defaults N A Load Setup Default values for all the setup questions F9 key can be used for this operation Load Custom Defaults N A Load custom defaults Save Custom Defaults N A Save custom defaults 9 6 Upgrading the BIOS 9 6 1 Preparing for the Upgrade Before you upgrade the BIOS prepare for the upgrade by recordi...

Page 70: ...ted type sys a 4 Press Enter 9 6 1 4 Flash Update Utility The BIOS flash utility suite is compatible with DOS WIN NT 4 0 2000 XP and LINUX operating environments The afuXXX AMI Firmware Update Utilities are required for BIOS updates 1 In DOS 1 The flash bootable disk must have ROM image and afudos 2 Enter in DOS 3 Run AFUDOS i ROM filename n p b n c 2 In WIN NT 4 0 2000 XP 1 The flash disk must ha...

Page 71: ...ble at the aliased addresses below 1 MB 9 6 3 Rolling BIOS and On line updates The Online Update nomenclature refers to the ability to update the BIOS while the server is online in operation as opposed to having to put the server out of operation while doing a BIOS update The Rolling BIOS nomenclature refers to the capability for having two copies of BIOS viz the one in use and the other to which ...

Page 72: ...e disk if there is no image file present the system will cycle through progress code F1 to EF 3 When F3 is displayed on port 80h the system will read the BIOS image file 4 The screen will display flash progress and show if NVRAM and CMOS have been destroyed 5 When recovery mode is complete the system will halt and the system can be powered off NOTE There are three different hot keys that can be in...

Page 73: ...File Limitations 1 Maximum Files supported 1000 files AMIBOOT 000 to AMIBOOT 999 Manually Recovering the BIOS A BIOS recovery can also be manually initiated This option would be used only when the BIOS is corrupt but the ROM checksum error does not occur during POST To manually initiate a BIOS recovery use the following steps 1 Power down and unplug the system from the AC power source 2 Move the r...

Page 74: ... 69 POST Error Beep Codes Beeps Error Message POST Progress Code Description 1 Fatal error System halted because of an unspecified fatal error that was detected 2 Processor error System halted because a fatal error related to a processor was detected 3 Memory error System halted because a fatal error related to the memory was detected 4 Motherboard error System halted because a fatal error related...

Page 75: ...t higher the granularity of information which could send on the progress port The progress codes may be reported by system BIOS or option ROMs The Response section in following table is divided in 3 different types Warning The message is displayed on screen and error is logged in SEL System will continue booting with degraded state User may want to replace erroneous unit Pause The message is displ...

Page 76: ... Pause 8194 CPUID Processor Family are different Pause 8195 Front Side Bus Speed mismatch System Halted Pause 8197 CPU Speed mismatch Pause 8300 Baseboard Management Controller failed to function Pause 8301 Front Panel Controller failed to Function Pause 84F2 Server Management Interface Failed Pause 84F3 BMC in Update Mode Pause 84F4 Sensor Data Record Empty Pause 84FF System Event Log Full Warnin...

Page 77: ...ferent devices through DIM See DIM Code Checkpoints section of document for more information 2C Initializes different devices Detects and initializes the video adapter installed in the system that have optional ROMs 2E Initializes all the output devices 31 Allocate memory for ADM module and uncompress it Give control to ADM module for initialization Initialize language and font modules for ADM Act...

Page 78: ... the programming of the MTRR s A8 Prepare CPU for OS boot including final MTRR values A9 Wait for user input at config display if needed AA Uninstall POST INT1Ch vector and INT09h vector De initializes the ADM module AB Prepare BBS for Int 19 boot AC End of POST initialization of chipset registers B1 Save system context for ACPI 00 Passes control to OS Loader typically INT19h 9 7 3 2 Boot Block In...

Page 79: ...y Leaves all RAM below 1MB Read Write including E000 and F000 shadow areas but closing SMRAM DA Restore CPUID value back into register Give control to BIOS POST ExecutePOSTKernel See POST Code Checkpoints section of document for more information 9 7 3 3 Boot Block Recovery Code Checkpoints The Boot block recovery code gets control when the BIOS determines that a BIOS recovery needs to occur becaus...

Page 80: ...nctions Reset Detect and Disable function 0 Static Device Initialization function 1 Boot Output Device Initialization function 2 Function 0 disables all device nodes PCI devices and PnP ISA cards It also assigns PCI bus numbers Function 1 initializes all static devices that include manual configured onboard peripherals memory and I O decode windows in PCI PCI bridges and noncompliant PCI devices S...

Page 81: ... a Red LED and each bit in the lower nibble is represented by a green LED If both bits are set in the upper and lower nibbles then both Red and Green LEDs are lit resulting in an Amber color If both bits are clear then the LED is off In the below example BIOS sends a value of ACh to the Diagnostic LED decoder The LEDs are decoded as follows Red bits 1010b Ah Green bits 1100b Ch Since the red bits ...

Page 82: ... code module Pass control to the POST code module 1Bh A R Off R Decompress the main system BIOS runtime code 1Ch A R Off A Pass control to the main system BIOS in shadow RAM E0h R R R Off Start of recovery BIOS Initialize interrupt vectors system timer DMA controller and interrupt controller E8h A R R Off Initialize extra module if present E9h A R R G Initialize floppy controller Eah A R A Off Try...

Page 83: ...M handler Initialize USB emulation 48h G R Off Off Validate NVRAM areas Restore from backup if corrupted 4Ah G R G Off Load defaults in CMOS RAM if bad checksum or CMOS clear jumper is detected 4Ch G A Off Off Validate date and time in RTC 4Eh G A G Off Determine number of micro code patches present 50h Off R Off R Load Micro Code To All CPUs 52h Off R G R Scan SMBIOS GPNV areas 54h Off A Off R Ea...

Page 84: ...a initialization has completed Checking for a locked key next 88h A Off Off Off Display USB devices 8Ah A Off G Off Verify RAM Size Checking for a memory size mismatch with CMOS RAM data next 8Ch A G Off Off Lock out PS 2 keyboard mouse if unattended start is enabled 8Eh A G G Off Init Boot Devices The adapter ROM had control and has now returned control to BIOS POST Performing any required proces...

Page 85: ...coder G Green R Red A Amber Hi Low Description Ach A G R Off Prepare USB controllers for operating system Aeh A G A Off One Beep to indicate end of POST No beep if silent boot is enabled 000h Off Off Off Off POST completed Passing control to INT 19h boot loader next ...

Page 86: ...e table reflect a common usage model operating at a higher than average stress levels Table 80 The Board Power Budget Power Supply Rail Voltages Units Watts AMPS FUNCTIONAL UNIT Utilization Power 3 3V 5 V 12 V 12V VRM 12v 5VSB BASEBOARD INPUT TOTALS 290 73W 6 26W 8 47W 6 38W 9 28W 0 05W 1 67 BASEBOARD DISCRETE TOTALS 50 32 02W 1 51 1 17 0 00 0 00 0 00 0 00 BASEBOARD CONVERTERS Efficiency 41 90W 3 ...

Page 87: ...V and 12V output voltages should start to rise approximately at the same time All outputs must rise monotonically The 5V output needs to be greater than the 3 3V output during any point of the voltage rise The 5V output must never be greater than the 3 3V output by more than 2 25V Each output voltage shall reach regulation within 50ms Tvout_on of each other during turn on of the power supply Each ...

Page 88: ...n regulation 2500 msec Tvout_holdup Time all output voltages stay within regulation after loss of AC 21 msec Tpwok_holdup Delay from loss of AC to de assertion of PWOK 20 msec Tpson_on_delay Delay from PSON active to output voltages within regulation limits 5 400 msec T pson_pwok Delay from PSON deactive to PWOK being de asserted 50 msec Tpwok_on Delay from output voltages within regulation limits...

Page 89: ...Dynamic Loading The output voltages shall remain within limits specified for the step loading and capacitive loading specified in the table below The load transient repetition rate shall be tested between 50Hz and 5kHz at duty cycles ranging from 10 90 The load transient repetition rate is only a test specification The Δ step load may occur anywhere within the MIN load to the MAX load conditions T...

Page 90: ... 50 60Hz No loss of function or performance 0 to 1 AC cycle 100 Nominal AC Voltage ranges 50 60Hz No loss of function or performance 1 AC cycle 10 Nominal AC Voltage ranges 50 60Hz Loss of function acceptable self recoverable Table 86 AC Line Surge Transient Performance AC Line Surge Duration Surge Operating AC Voltage Line Frequency Performance Criteria Continuous 10 Nominal AC Voltages 50 60Hz N...

Page 91: ...on any signal with respect to ground 0 3 V to Vdd 0 3V 2 3 3 V Supply Voltage with Respect to ground 0 3 V to 3 63 V 5 V Supply Voltage with Respect to ground 0 3 V to 5 5 V Notes 1 Chassis design must provide proper airflow to avoid exceeding the processor maximum case temperature 2 VDD means supply voltage for the device 11 1 Mean Time Between Failures MTBF Test Results This section provides res...

Page 92: ...N 22 Monitors 1 8V DDRII power LM96000 P5V PIN 20 Monitors 5V LM96000 Fan Speed PWM1 PIN 24 Controls system front fans JP5J1 JP5J2 JP7A1 JP6A1 J6J3 J6J1 J6J4 J6J2 LM96000 PWM2 PIN 10 Controls CPU fans J7A1 LM96000 PWM3 PIN 13 N A LM96000 TACH1 PIN 11 Monitors CPU fan J7A1 LM96000 TACH2 PIN 12 Monitors SYS FAN_3 JP5J1 LM96000 TACH3 PIN 9 Monitors SYS FAN_4 JP5J2 LM96000 FANIN0 PIN 66 Monitors SYS F...

Page 93: ...rol Block Diagram LM96000 Super IO PC87427 CPU FAN SYS FAN3 SYS FAN4 SYS FAN2 SYS FAN1 J7A11 SYS FAN5 A B SYS FAN6 A B SYS FAN8 A B SYS FAN7 A B JP5J1 JP5J2 JP7A1 JP6A1 J6J1 J6J2 J6J4 J6J3 PWM1 PWM2 TACH1 TACH2 TACH3 FANIN0 FANIN1 FANIN2 FANIN3 FANIN4 FANIN5 FANIN6 FANIN7 PWM CKT FAN SPEED CNTL1 ...

Page 94: ...e The SE7221BK1 E has been has been tested and verified to comply with the following electromagnetic compatibility EMC regulations when installed in a compatible Intel host system For information on compatible host system s contact your local Intel representative FCC Class A Verification Radiated Conducted Emissions USA ICES 003 Class A Radiated Conducted Emissions Canada CISPR 22 3rd Edition Clas...

Page 95: ...ed operation For questions related to the EMC performance of this product contact Intel Corporation 5200 N E Elam Young Parkway Hillsboro OR 97124 1 800 628 8686 This equipment has been tested and found to comply with the limits for a Class A digital device pursuant to Part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference in a residential ...

Page 96: ...d grounded Operation with cables connected to peripherals that are not shielded and grounded may result in interference to radio and TV reception 13 2 2 INDUSTRY CANADA ICES 003 This digital apparatus does not exceed the Class A limits for radio noise emissions from digital apparatus set out in the interference causing equipment standard entitled Digital Apparatus ICES 003 of the Canadian Departme...

Page 97: ...sentative or dealer for a list of approved devices WARNING Danger of explosion if battery is incorrectly replaced Replace only with the same or equivalent type recommended by the equipment manufacturer Discard used batteries according to manufacturer s instructions ADVARSEL Lithiumbatteri Eksplosionsfare ved fejlagtig håndtering Udskiftning må kun ske med batteri af samme fabrikat og type Levér de...

Page 98: ... configured from the factory is shown in the table below Table 90 MTBF Data Product Code Calculated MTBF Operating Temperature SE7221BK1 TBD hours 35 degrees C SE7221BK1LX TBD hours 35 degrees C 13 5 Mechanical Specifications The following figure shows the Intel Server Board SE7221BK1 E mechanical drawing This drawing will be updated in a future revision of this document ...

Page 99: ...SE7221BK1 E Technical Product Specification 87 Figure 11 SE7221BK1 E Server Board Mechanical Drawing ...

Page 100: ... The following figures show the I O shield mechanical drawings for use in pedestal mount applications such as the Intel Server Chassis SC5200 for both sku s SE7221BK1 E and SE7221BK1 E LX Figure 12 sku 1 Pedestal mount I O shield mechanical drawing ...

Page 101: ...SE7221BK1 E Technical Product Specification 89 Figure 13 sku 2 Pedestal mount I O shield mechanical drawing ...

Page 102: ......

Page 103: ...the PC AT compatible region of battery backed 128 bytes of memory which normally resides on the server board DCD Data Carrier Detect DMA Direct Memory Access DMTF Distributed Management Task Force ECC Error Correcting Code EMC Electromagnetic Compatibility EPS External Product Specification ESCD Extended System Configuration Data FDC Floppy Disk Controller FIFO First In First Out FRU Field replace...

Page 104: ...st PWM Pulse Width Modulator RAIDIOS RAID I O Steering RAM Random Access Memory RI Ring Indicate RISC Reduced instruction set computing RMCP Remote Management Control Protocol ROM Read Only Memory RTC Real Time Clock SBE Single Bit Error SCI System Configuration Interrupt SDR Sensor Data Record SDRAM Synchronous Dynamic RAM SEL System event log SERIRQ Serialized Interrupt Requests SERR System Erro...

Page 105: ...E Technical Product Specification Glossary III Term Definition USB Universal Serial Bus VGA Video Graphic Adapter VID Voltage Identification VRM Voltage Regulator Module Word 16 bit quantity ZCR Zero Channel RAID ...

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