Intel SC450NX - Server Platform - 0 MB RAM, Product Manual

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Interrupts
The table below recommends the logical interrupt mapping of interrupt sources; it reflects a typical
configuration, but these interrupts can be changed by the user. Use the information to determine
how to program each interrupt. The actual interrupt map is defined using configuration registers in
the PIIX4E and the I/O controller. I/O Redirection Registers in the I/O APIC are provided for each
interrupt signal; the signals define hardware interrupt signal characteristics for APIC messages sent
to local APIC(s).
✏
NOTE
To disable either IDE controller and reuse the interrupt: if you plan to
disable either IDE controller to reuse the interrupt for that controller, you
must physically unplug the IDE cable from the board connector (IDE0) if a
cable is present. Simply disabling the drive by configuring the SSU option
does not make the interrupt available.
Table 53. Interrupts
Interrupt I/O APIC level Description
INTR INT0 Processor interrupt
NMI N/A NMI from PIC to processor
IRQ1 INT1 Keyboard interrupt
Cascade INT2 Interrupt signal from second 8259 in PIIX4E
IRQ3 INT3 Serial port A or B interrupt from SIO device (user can configure)
IRQ4 INT4 Serial port A or B interrupt from SIO device (user can configure)
IRQ5 INT5 Parallel port II
IRQ6 INT6 Diskette port
IRQ7 INT7 Parallel port
IRQ8_L INT8 RTC interrupt
IRQ9 INT9 Signal control interrupt (SCI) used by ACPI-compliant OS
IRQ10 INT10
IRQ11 INT11
IRQ12 INT12 Mouse interrupt
INT13
IRQ14 INT14 Compatibility IDE interrupt from primary channel IDE devices 0 and 1
IRQ15 INT15
SMI_L System management interrupt—general purpose indicator sourced
by the PIIX4E and BMC through the PID to the processors