Intel PXA27x Series, User Manual, Page: 85 / 88

Intel
®
PXA27x Processor Developer’s Kit - User’s Guide 85
3.6 Programming Flash Memory and Logic Devices
This section provides instructions for programming the flash memory and complex programmable
logic devices (CPLDs) in the kit:
•
Section 3.6.1 — Flash Memory . See Section 3.6.1, “Flash Memory” on page 86
•
Section 3.6.2 — CPLD1 (Processor Card) : Intel
®
PXA270 Processor memory-bus control and
power sequencing logic. See Section 2.3.3, “Programmable Daughter Card Logic (CPLD1)”
on page 39 .
•
Section 3.6.3 — CPLD2 (Main Board) : I/O main board memory-bus control logic. See
Section 2.2.5, “Programmable Main Board Logic (CPLD2)” on page 24 .
•
Section 3.6.4 — FPGA Configuration EEPROM (Main Board) : platform-level registers,
interrupts, and control logic. See Section 2.2.4, “Main Board Registers and Interrupt
Controller (FPGA)” on page 23 .
Programming these devices takes place via the Intel
®
PXA270 Processor JTAG interface, using the
Intel
®
JTAG Cable (JTAG cable) and a host computer with Windows* XP or Windows* 2000
installed as the operating system.
3.6.0.1 Preparing the Hardware
The hardware for programming flash memory and logic devices consists of two cables and an
interface module. To install thethis hardware and prepare the kit for programming, follow these
steps:
1. Turn off the kit power.
2. Attach the 25-pin parallel-port cable between the host computer’s parallel port and the
matching connector on the interface card.
3. Attach the 20-pin ribbon cable between the matching connector on the interface card and the
JTAG connector (J3) on the Intel
®
PXA270 Processor (keyed to avoid errors).
Note: The interface card draws a few milliamps of 3.3-volt power from the Intel
®
PXA270 Processor on
pin 1 of the JTAG connector.
3.6.0.2 Preparing the Host Computer
The flash-memory programming software, JFlashMM, requires that a parallel port device driver be
installed on the host computer when using Windows* NT or Windows* 2000. To configure the
host with this device driver, follow these steps:
1. Configure the parallel port for ECP mode.
2. Install the JFlashMM software by following the instructions in the JFlashMM release notes.
3.6.0.3 Obtaining the Required Programming Files
Programming the CPLDs or the FPGA configuration EEPROM requires that the specific
programming files be installed on the host computer. To obtain these files, contact the appropriate
Intel field sales representative (see Intel’s web site at www.intel.com for a list of the
representatives).