Intel PXA27x Series, User Manual

Page: 81 / 88

Intel
®
PXA27x Processor Developer’s Kit - User’s Guide 81
3.5 General Purpose Input/Output (GPIO)
The interfaces between the main board and the Intel
®
PXA270 Processor take place through the
Intel
®
PXA270 Processor GPIO pins, as shown in Table 33 .
For instructions on programming the GPIO pins, refer to the GPIO chapter in the Intel
®
PXA27x
Processor Family Developer’s Manual .
Note: In the table, the direction shown is relative to the processor .
Table 33. GPIO Map (Sheet 1 of 4)
GPIO Alternate Functions Direction Description
0 GPIO0 I Platform interrupt source from FPGA
1 GPIO1 I Platform interrupt source from main board switch SW21
2 SYS_EN O Power system enable
3 PWR_SCL I/O I
2
C power management clock
4 PWR_SDA I/O I
2
C power management data
5 PWR_CAP0 — Sleep/deep-sleep regulator capacitor
6 PWR_CAP1 — Sleep/deep-sleep regulator capacitor
7 PWR_CAP2 — Sleep/deep-sleep regulator capacitor
8 PWR_CAP3 — Sleep/deep-sleep regulator capacitor
9 CLK_PIO I/O
Processor clock — direction depends on clock source (crystal,
oscillator, SMA, Baseband)
10 CLK_TOUT O 32-kHz clock
11 SSPRXD2 I SSP2 Receive
12 DD[7] I Camera Interface Data
13 SSPTXD2 O SSP2 Transmit
14 L_VSYNC I Refresh sync signal from the LCD panel with internal frame buffer
15 nCS1 O Static chip select for flash
16 PWM_OUT0 O Pulse-width-modulated output — routed to LCD
17
PWM_OUT1 /
CIF_DD[6]
O Pulse-width-modulated output / Camera Interface Data
18 RDY I Variable-latency I/O device ready for inserting wait states
19 L_CS O LCD chip select for panels with an internal frame buffer
20 MBREQ I Alternate Bus Mastering Request
21 MBGNT O Alternate Bus Mastering Grant
22 SSPSCLK2 I/O SSP2 Clock
23 CIF_MCLK O Camera Interface Module Clock
24 CIF_FV I Camera Interface Frame Sync
25 CIF_LV I Camera Interface Line Sync
26 CIF_PCLK I Camera Interface Pixel Clock
27 CIF_DD[0] I Camera Interface Data