Intel PXA27x Series, User Manual

Page: 63 / 88

Intel
®
PXA27x Processor Developer’s Kit - User’s Guide 63
3.2.2.9 Platform Interrupt Mask/Enable Register (INTMSKENA)
INTMSKENA, defined in Table 27 , provides for masking and enabling the interrupts listed in the
table. To enable an interrupt , set its corresponding bit. To mask it , clear its bit.
For details of the kit interrupt controller, see Section 3.4 .
Table 26 defines the high bit definitions. (31-16).
Table 27 defines the low bit definitions.(15-0).
Note: Ignore reads from reserved bits. Write 0b0 to reserved bits.
Table 26. INTMSKEN Bit Definitions High Bits
Physical Address: 0x0800_00C0 INTMSKEN Intel
®
PXA27x Processor Developer’s Kit
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Reserved
INT
_
Mx
BT
_RI_IN
T
BT
_DTR_
INT
PMC_IRQ
Reset ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0
Bits Name Access Description
31-20 reserved R/W reserved
19 INT_Mx R/W Graphics Accelerator Interrupt Request
18 BT_RI_INT R/W Bluetooth Ring Indicator Interrupt Request
17 BT_DTR_INT R/W Bluetooth UART Data Terminal Ready Interrupt Request
16 PMC_IRQ R/W Power Management IC Interrupt Request
Table 27. INTMSKEN Bit Definitions Low Bits (Sheet 1 of 2)
Physical Address: 0x0800_00C0 INTMSKEN Intel
®
PXA27x Processor Developer’s Kit
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
S1_IR
Q
S1_STSC
H
G
S1_
C
D
rese
rv
ed
S0_IR
Q
S0_STSC
H
G
S0_
C
D
rese
rv
ed
nEXBRD_INT
MSINS
PENIRQ
AC97
ETH
E
RNET
USB
C
USIM
MMC
Reset 0 0 0 ? 0 0 0 ? 0 0 0 0 0 0 0 0
Bits Name Access Description
15 S1_IRQ R/W PCMCIA socket 1 interrupt request (IRQ)
14 S1_STSCHG R/W PCMCIA socket 1 status changed
13 S1_CD R/W PCMCIA socket 1 card detection
12 — — reserved
11 S0_IRQ R/W PCMCIA socket 0 IRQ
10 S0_STSCHG R/W PCMCIA socket 0 status changed