Intel
®
PXA27x Processor Developer’s Kit - User’s Guide
23
Note:
SW2 does not reset the system when docked to the main board.
•
Slide the main board switch SW9 to the NO DOT position. This forces the FPGA to initiate a
new configuration load and asserts nRESET via FPGA_DONE.
Reset remains asserted until SW9 is returned to the DOT position.
•
Set the SYSRESET bit in the Miscellaneous Write Register 1. This pulses the nSYS_RST
signal and forces the PMIC board to assert nRESET. The SYSRESET bit is automatically
cleared upon reset.
2.2.3
Flash Memory and Boot ROM
Two Synchronous Intel StrataFlash
®
memory (K3) devices provide 32 Mbytes of flash memory on
the main board. This bank is meant for asynchronous usage, is slower than the bank on the
processor card, and is intended primarily for ease of software development.
By default, the kit chip-selects operate as follows:
•
nCS0, which is always the boot segment in the Intel
®
PXA270 Processor memory map,
connects to the processor card’s flash-memory bank.
•
nCS1 connects to the main board flash-memory bank.
Switch SW7 can swap nCS0 and nCS1, so that the main board flash-memory bank serves as the
boot source. SW7 must be set to the desired position
before
applying power to the main board,
since it normally gets read into the System Configuration Register only at boot time. For more
information, see
Section 3.2.1.1, “System Configuration Register (SCR)” on page 51
The default bus width for both the main board and processor card’s flash-memory banks is 32 bits.
The main board flash-memory bank, but
not
the Synchronous Intel StrataFlash
®
Wireless memory
(L18) processor card flash-memory bank, can optionally be set to operate on a 16-bit bus. If it is
necessary to boot using a 16-bit bus, two switches must be changed, as follows.
1. Set main board switch SW7 to use the main board bank as the boot source.
2. Set the processor card’s switch SW8 for 16-bit boot-bus width.
For more information on programming flash memory, see the JFlash release notes.
2.2.4
Main Board Registers and Interrupt Controller (FPGA)
A Xilinx 2.5-volt field-programmable gate array implements the platform-level registers and
interrupt controller. The FPGA obtains its configuration data from an EEPROM. The extra pins
from the FPGA have been routed to the FPGA header, J20. You can reprogram the FPGA to take
advantage of these pins. For information on programming the EEPROM, see
“Programming Flash Memory and Logic Devices” on page 85
The main board switch SW9 works within the system reset structure by forcing an FPGA
configuration load from the EEPROM. For more information, see
LED D1 comes on when the FPGA comes out of reset. After that, it is programmable via
Miscellaneous Write Register 1.
Section 3.2, “Platform-Level Registers” on page 49
describes the registers and their programming.
Section 3.4, “Developer’s Kit Platform-Level Interrupts” on page 78
describes the interrupt
controller and its programming.
Summary of Contents for PXA27x Series
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