Intel
®
PXA27x Processor Developer’s Kit - User’s Guide
21
2.2.1
Power Input and Voltage Regulation
The main board derives its power from an external 110 VAC to +12 VDC adapter rated at
6.0 ADC. The +12 VDC main board input is fuse-protected. Switch SW22 turns power to the board
on and off. Several LEDs indicate the states of different power-supply domains — for a listing of
the indicators, see
J42 on the main board a12 VDC from the power adapter.
The main board uses Linear Technologies regulators to supply the 2.5 VDC, 3.3 VDC, 5 VDC, and
12 VDC power domains. The main board can also supply power to the Intel
®
PXA270 Processor
(see
).
2.2.2
System Reset
This section describes the reset structure and provides instructions for user-initiated reset.
2.2.2.1
Structure and Operation
For this discussion,
depicts the reset logic and structure. The following sequence occurs
after power is applied to the system or after a user-initiated reset:
1. The Intel
®
PXA270 Processor asserts nRESET_OUT, which generates the following resets:
a. On the main board, CPLD2 resets the expansion card, Ethernet controller, FPGA-based
platform registers, and flash-memory bank.
2. Voltage supervisor U18 monitors the Intel
®
PXA270 Processor’s VCC RTC supply as it ramps
up.
This supply, from the PMIC card is always enabled, regardless of any low-power state of the
processor.
3. A minimum of 140 ms after the VCC RTC supply has stabilized, the open-drain supervisor
outputs release nTRST and nRESET, thus deasserting nTRST through a pull-up resistor. This
allows use of the processor JTAG port.
4. nRESET de-asserts through a pull-up resistor after the field-programmable gate array (FPGA;
see section
) downloads its configuration data from the FPGA configuration
PROM (U18) and releases FPGA_DONE. Decreasing the data rate of the FPGA configuration
process can delay the release of FPGA_DONE.
5. The Intel
®
PXA270 Processor completes its hardware reset procedure and deasserts
nRESET_OUT. On the daughter card, the Intel
®
Mobile Scalable Link (Intel
®
MSL)
MSL_nRESET flash-memory reset and the RS-232 ForceOff are released. The first instruction
is fetched from the memory attached to chip select nCS[0].
6. If a Intel
®
PXA270 Processor is present (nDRCD_PRES low), CPLD2 on the main board
releases the resets for the Ethernet controller, FPGA-based platform registers, main board
flash-memory bank, and the expansion card.
If no Intel
®
PXA270 Processor is detected, the main board remains in the reset state.
Summary of Contents for PXA27x Series
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