Intel M50CYP2SB Series, Technical Specification

Page: 119 / 160

Intel® Server Board M50CYP2SB Family Technical Product Specification
119
Post
Code
(Hex)
Upper Nibble Lower Nibble
Description
8h 4h 2h 1h 8h 4h 2h 1h
93 1 0 0 1 0 0 1 1 DXE PCI Bus HPC Init
94 1 0 0 1 0 1 0 0 DXE PCI Bus enumeration
95 1 0 0 1 0 1 0 1 DXE PCI Bus resource requested
96 1 0 0 1 0 1 1 0 DXE PCI Bus assign resource
97 1 0 0 1 0 1 1 1 DXE CON_OUT connect
98 1 0 0 1 1 0 0 0 DXE CON_IN connect
99 1 0 0 1 1 0 0 1 DXE SIO Init
9A 1 0 0 1 1 0 1 0 DXE USB start
9B 1 0 0 1 1 0 1 1 DXE USB reset
9C 1 0 0 1 1 1 0 0 DXE USB detect
9D 1 0 0 1 1 1 0 1 DXE USB enable
A1 1 0 1 0 0 0 0 1 DXE IDE begin
A2 1 0 1 0 0 0 1 0 DXE IDE reset
A3 1 0 1 0 0 0 1 1 DXE IDE detect
A4 1 0 1 0 0 1 0 0 DXE IDE enable
A5 1 0 1 0 0 1 0 1 DXE SCSI begin
A6 1 0 1 0 0 1 1 0 DXE SCSI reset
A7 1 0 1 0 0 1 1 1 DXE SCSI detect
A8 1 0 1 0 1 0 0 0 DXE SCSI enable
AB 1 0 1 0 1 0 1 1 DXE SETUP start
AC 1 0 1 0 1 1 0 0 DXE SETUP input wait
AD 1 0 1 0 1 1 0 1 DXE Ready to Boot
AE 1 0 1 0 1 1 1 0 DXE Legacy Boot
AF 1 0 1 0 1 1 1 1 DXE Exit Boot Services
B0 1 0 1 1 0 0 0 0 RT Set Virtual Address Map Begin
B1 1 0 1 1 0 0 0 1 RT Set Virtual Address Map End
B2 1 0 1 1 0 0 1 0 DXE Legacy Option ROM init
B3 1 0 1 1 0 0 1 1 DXE Reset system
B4 1 0 1 1 0 1 0 0 DXE USB Hot plug
B5 1 0 1 1 0 1 0 1 DXE PCI BUS Hot plug
B8 1 0 1 1 1 0 0 0 PWRBTN Shutdown
B9 1 0 1 1 1 0 0 1 SLEEP Shutdown
C0 1 1 0 0 0 0 0 0 End of DXE
C7 1 1 0 0 0 1 1 1 DXE ACPI Enable
0 0 0 0 0 0 0 0 0 Clear POST Code
S3 Resume
E0 1 1 1 0 0 0 0 0 S3 Resume PEIM (S3 started)
E1 1 1 1 0 0 0 0 1 S3 Resume PEIM (S3 boot script)
E2 1 1 1 0 0 0 1 0 S3 Resume PEIM (S3 Video Repost)
E3 1 1 1 0 0 0 1 1 S3 Resume PEIM (S3 OS wake)