Intel® Server Board M50CYP2SB Family Technical Product Specification
50
Memory RAS Feature
Description
Standard
Advanced
MEMHOT Pin Support for
Error Reporting
MEMHOT pin can be configured as an output and used to notify if
DIMM is operating within the target temperature range. Used to
implement “Memory Thermal Throttling”.
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Notes:
Population Rules and BIOS Setup for Memory RAS
•
Memory sparing and memory mirroring options are enabled in BIOS Setup.
•
Memory sparing and memory mirroring options are mutually exclusive in this product. Only one
operating mode at a time may be selected in BIOS Setup.
•
If a RAS mode has been enabled and the memory configuration is not able to support it during boot,
the system will fall back to independent channel mode and log and display errors.
•
Rank sparing mode is only possible when all channels that are populated with memory have at least
two single-rank or double-rank DIMMs installed, or at least one quad-rank DIMM installed on each
populated channel.
•
Memory mirroring mode requires that for any channel pair that is populated with memory, the
memory population on both channels of the pair must be identically sized.
•
The Intel® Optane™ persistent memory 200 series RAS features listed in the following table are
integrated into the system memory RAS features.
The following table lists additional memory RAS feat
ures specific to the Intel® Optane™ persistent memory
200 series memory.
These features are managed by the processor’s IMC
.
Table 12
. Intel® Optane™
Persistent Memory 200 Series RAS Features
Memory RAS Feature
Description
DIMM Error Detection and
Correction
Protects against random bit failures across media devices.
DIMM Device Failure Recovery
(Single Device Data Correction
(SDDC))
Corrects errors resulting from the failure of a single media device.
DIMM Package Sparing (Double
Device Data Correction (DDDC))
Achieved by a spare device on the DIMM and erasure decoding.
DIMM Patrol Scrubbing
Proactively searches the DIMM memory, repairing correctable errors. This can prevent
correctable errors from becoming uncorrectable due to accumulation of failed bits.
DIMM Address Error Detection
Ensures the correctness of addresses when data is read from media devices.
DIMM Data Poisoning
Mechanism to contain, and possibly recover from, uncorrectable data errors.
Depending on the mode used, poisoning has different reset behavior:
• In
Memory mode, poison is cleared after reset.
• In App Direct
mode, poison is not cleared with reset.
DIMM Viral
Ensures that potentially corrupted data is not committed to persistent memory in App Direct
and is supported only in tandem with poison. Viral mode does not apply to memory mode.
DIMM Address Range Scrub (ARS)
Obtains the healthy memory media range before assigning it to a persistent memory region.
DDR-T Command and Address
Parity Check and Retry
Host retries a CMD/ADDR transaction if the DIMM controller detects a parity error and
initiates an error flow.
DDR-T Read/Write Data ECC
Check and Retry
Host continuously retries a data transaction as long as the DIMM controller detects an ECC
error and initiates an error flow.
Faulty DIMM Isolation
Identifies a specific failing DIMM enabling replacement of only the DIMM that has failed.
