Intel® Server Board M50CYP2SB Family Technical Product Specification
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Table 11. Memory RAS Features
Memory RAS Feature
Description
Standard
Advanced
Partial Cache-Line Sparing
(PCLS)
Allows replacing failed single bit within a device using spare capacity
available within the processor’s integrated memory controller (IMC).
Up to 16 failures allowed per memory channel and no more than one
failure per cache line. After failure is detected, replacement is
performed at a nibble level. Supported with x4 DIMMs only.
√
√
Device Data Correction
Single Device Data Correction (SDDC) via static virtual lockstep
Supported with x4 DIMMs only.
√
√
Adaptive Data Correction
–
Single Region (ADC-SR) via adaptive
virtual lockstep (applicable to x4 DRAM DIMMs). Cannot be enabled
with “Memory Multi
-
Rank Sparing” or “Write Data CRC Check and
Retry.”
√
√
Adaptive Double Data Correction
–
Multiple Region (ADDDC-MR, + 1)
Supported with x4 DIMMs only.
−
√
DDR4 Command/Address
(CMD/ADDR) Parity Check and
Retry
DDR4 technology based CMD/ADDR parity check and retry with
CMD/ADDR parity error “address” logging and CMD/ADDR retry.
√
√
DDR4 Write Data CRC Check
and Retry
Checks for CRC mismatch and sends a signal back to the processor
for retry. Cannot be enabled with “ADC
-
SR” or “ADDDC
-
MR, +1.”
√
√
Memory Data Scrambling with
Command and Address
Scrambles the data with address and command in “write cycle” and
unscrambles the data in “read cycle”. Addresses
reliability by
improving signal integrity at the physical layer. Additionally, assists
with detection of an address bit error.
√
√
Memory Demand and Patrol
Scrubbing
Demand scrubbing is the ability to write corrected data back to the
memory once a correctable error is detected on a read transaction.
Patrol scrubbing proactively searches the system memory, repairing
correctable errors. Prevents accumulation of single-bit errors.
√
√
Memory Mirroring
Full memory mirroring: An intra-IMC method of keeping a duplicate
(secondary or mirrored) copy of the contents of memory as a
redundant backup for use if the primary memory fails. The mirrored
copy of the memory is stored in memory of the same processor
socket's IMC. Dynamic (without reboot) failover to the mirrored
DIMMs is transparent to the operating system and applications.
√
√
Address range/partial memory mirroring: Provides further intra
socket granularity to mirroring of memory. This allows the firmware
or OS to determine a range of memory addresses to be mirrored,
leaving the rest of the memory in the socket in non-mirror mode.
−
√
DDR Memory Multi-Rank
Memory Sparing
Up to two ranks out of a maximum of eight ranks can be assigned as
spare ranks.
Cannot be enabled with “ADC
-
SR”, “ADDDC
-
MR, +1”, and
“Memory Mirroring”.
√
√
Memory SMBus* Hang
Recovery
Allows system recovery if the SMBus fails to respond during runtime,
thus, preventing system crash.
√
√
Memory Disable and Map Out
for Fault Resilient Boot (FRB)
Allows memory initialization and booting to the operating system
even when memory fault occurs.
√
√
Post Package Repair (PPR)
PPR offers additional spare capacity within the DDR4 DRAM that can
be used to replace faulty cell areas detected during system boot
time.
√
√
Memory Thermal Throttling
Management controller monitors the memory DIMM temperature
and can temporarily slow down the memory access rates to reduce
the DIMM temperature if needed.
√
√
