Intel I7-900 DEKSTOP SPECIFICATION, Datasheet

Page: 72 / 98

Register Description
72 Datasheet
2.10.16 MC_CHANNEL_0_RCOMP_PARAMS
MC_CHANNEL_1_RCOMP_PARAMS
MC_CHANNEL_2_RCOMP_PARAMS
This register contains parameters that specify Rcomp timings.
2.10.17 MC_CHANNEL_0_ODT_PARAMS1
MC_CHANNEL_1_ODT_PARAMS1
MC_CHANNEL_2_ODT_PARAMS1
This register contains parameters that specify ODT timings. All values are in DCLK.
Device: 4, 5, 6
Function: 0
Offset: 98h
Access as a Dword
Bit Type
Reset
Value
Description
16 RW 1
RCOMP_EN.
Enable Rcomp. When set, the Integrated Memory Controller will do the
programmed blocking of requests and send indications.
15:10 RW 2
RCOMP_CMD_DCLK.
Delay from the start of an RCOMP command blocking period in which the
command rcomp update is done. Program this field to 15 for all configurations.
9:4 RW 9
RCOMP_LENGTH.
Number of Dclks during which all commands are blocked for an RCOMP update.
Data RCOMP update is done on the last DCLK of this period. Program this field
to 31 for all configurations.
3:0 RW 0
RCOMP_INTERVAL.
Duration of interval between Rcomp in increments of tRefI. Register value is
tRefI-1. For example a setting of 0 will produce an interval of tRefI.
Device: 4, 5, 6
Function: 0
Offset: 9Ch
Access as a Dword
Bit Type
Reset
Value
Description
26:24 RW 0
TAOFD.
ODT turn off delay.
23:20 RW 6
MCODT_DURATION.
Controls the duration of MC ODT activation. BL/2 + 2.
19:16 RW 4
MCODT_DELAY.
Controls the delay from Rd CAS to MC ODT activation. This value is tCAS-1.
15:12 RW 5
ODT_RD_DURATION.
Controls the duration of Rd ODT activation. This value is BL/2 + 2.
11:8 RW 0
ODT_RD_DELAY.
Controls the delay from Rd CAS to ODT activation. This value is tCAS-tWL.
7:4 RW 5
ODT_WR_DURATION.
Controls the duration of Wr ODT activation. value is BL/2 + 2.
3:0 RW 0
ODT_WR_DELAY.
Controls the delay from Wr CAS to ODT activation. This value is always 0.