Datasheet
65
Register Description
2.10.8
MC_CHANNEL_0_MRS_VALUE_2
MC_CHANNEL_1_MRS_VALUE_2
MC_CHANNEL_2_MRS_VALUE_2
The initial MRS register values for MR2. This register also contains the values used for
RC0 and RC2 writes for registered DIMMs. These values are used during the automated
training sequence when MRS writes or registered DIMM RC writes are used. The RC
fields do not need to be programmed if the address inversion and 3T/1T transitions are
disabled.
2.10.9
MC_CHANNEL_0_RANK_PRESENT
MC_CHANNEL_1_RANK_PRESENT
MC_CHANNEL_2_RANK_PRESENT
This register provides the rank present vector.
Device:
4, 5, 6
Function: 0
Offset:
74h
Access as a Dword
Bit
Type
Reset
Value
Description
23:20
RW
0
RC2.
The values to write to the RC2 register on RDIMMS. This value will be written
whenever 3T or 1T timings are enabled by hardware. For this reason bit 1 of the
RC2 field (bit 21 of this register) will be controlled by hardware. [23:22] and
[20] will be driven with the RDIMM register write command for RC2.
19:16
RW
0
RC0.
The values to write to the RC0 register on RDIMMS. This value will be written
whenever address inversion is enabled or disabled by hardware. For this reason
bit 0 of the RC0 field (bit 16 of this register) will be controlled by hardware.
[19:17] will be driven with the RDIMM register write command for RC0.
15:0
RW
0
MR2.
The values to write to MR2 for A15:A0.
Device:
4, 5, 6
Function: 0
Offset:
7Ch
Access as a Dword
Bit
Type
Reset
Value
Description
7:0
RW
0
RANK_PRESENT.
Vector that represents the ranks that are present. Each bit represents a logical
rank. When two or fewer DIMMs are present, [3:0] represents the four possible
ranks in DIMM0 and [7:4] represents the ranks that are possible in DIMM1.
When three DIMMs are present, then the following applies:
[1:0] represents ranks 1:0 in Slot 0
[3:2] represents ranks 3:2 in Slot 1
[5:4] represents ranks 5:4 in Slot 2
Summary of Contents for I7-900 DEKSTOP SPECIFICATION
Page 10: ...10 Datasheet...
Page 14: ...Introduction 14 Datasheet...
