Intel I7-900 DEKSTOP SPECIFICATION Datasheet Download | Manualshive

Page: 58 / 98

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Register Description

58

Datasheet

2.9.2

TAD_INTERLEAVE_LIST_0, TAD_INTERLEAVE_LIST_1

TAD_INTERLEAVE_LIST_2, TAD_INTERLEAVE_LIST_3

TAD_INTERLEAVE_LIST_4, TAD_INTERLEAVE_LIST_5

TAD_INTERLEAVE_LIST_6, TAD_INTERLEAVE_LIST_7

TAD DRAM package assignments. When the corresponding DRAM_RULE hits, a 3-bit
number (determined by mode) is used to index into the Interleave_List Branches to
determine which channel the DRAM request belongs to.

Device:

3

Function: 1

Offset:

C0h, C4h, C8h, CCh, D0h, D4h, D8h, DCh

Access as a Dword

Bit

Type

Reset

Value

Description

29:28

RW

-

Logical Channel7.
Index 111 of the Interleave List. Bits determined from the matching

TAD_DRAM_RULE mode.
00 = Logical channel 0
01 = Logical channel 1
10 = Logical channel 2
11 = Reserved

25:24

RW

-

Logical Channel6.
Index 110 of the Interleave List. Bits determined from the matching

TAD_DRAM_RULE mode.
00 = Logical channel 0
01 = Logical channel 1
10 = Logical channel 2
11 = Reserved

21:20

RW

-

Logical Channel5.
Index 101 of the Interleave List. Bits determined from the matching

TAD_DRAM_RULE mode.
00 = Logical channel 0
01 = Logical channel 1
10 = Logical channel 2
11 = Reserved

17:16

RW

-

Logical Channel4.
Index 100 of the Interleave List. Bits determined from the matching

TAD_DRAM_RULE mode.
00 = Logical channel 0
01 = Logical channel 1
10 = Logical channel 2
11 = Reserved

13:12

RW

-

Logical Channel3.
Index 011 of the Interleave List. Bits determined from the matching

TAD_DRAM_RULE mode.
00 = Logical channel 0
01 = Logical channel 1
10 = Logical channel 2
11 = Reserved

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Summary of Contents for I7-900 DEKSTOP SPECIFICATION

Page 1: ...Document Number 320835 003 Intel Core i7 900 Desktop Processor Extreme Edition Series and Intel Core i7 900 Desktop Processor Series Datasheet Volume 2 October 2009...

Page 2: ...g Technology requires a computer system with a processor supporting HT Technology and an HT Technology enabled chipset BIOS and operating system Performance will vary depending on the specific hardwar...

Page 3: ...6 4 SAD_SMRAM 44 2 6 5 SAD_PCIEXBAR 45 2 6 6 SAD_DRAM_RULE_0 SAD_DRAM_RULE_1 SAD_DRAM_RULE_2 SAD_DRAM_RULE_3 SAD_DRAM_RULE_4 SAD_DRAM_RULE_5 SAD_DRAM_RULE_6 SAD_DRAM_RULE_7 45 2 6 7 SAD_INTERLEAVE_LIS...

Page 4: ...7 MC_CHANNEL_0_MRS_VALUE_0_1 MC_CHANNEL_1_MRS_VALUE_0_1 MC_CHANNEL_2_MRS_VALUE_0_1 64 2 10 8 MC_CHANNEL_0_MRS_VALUE_2 MC_CHANNEL_1_MRS_VALUE_2 MC_CHANNEL_2_MRS_VALUE_2 65 2 10 9 MC_CHANNEL_0_RANK_PRES...

Page 5: ...77 2 10 28 MC_CHANNEL_0_EW_BGF_SETTINGS MC_CHANNEL_1_EW_BGF_SETTINGS MC_CHANNEL_2_EW_BGF_SETTINGS 78 2 10 29 MC_CHANNEL_0_EW_BGF_OFFSET_SETTINGS MC_CHANNEL_1_EW_BGF_OFFSET_SETTINGS MC_CHANNEL_2_EW_BG...

Page 6: ...2_6 MC_RIR_LIMIT_CH2_7 88 2 12 2 MC_RIR_WAY_CH0_0 MC_RIR_WAY_CH0_1 MC_RIR_WAY_CH0_2 MC_RIR_WAY_CH0_3 MC_RIR_WAY_CH0_4 MC_RIR_WAY_CH0_5 MC_RIR_WAY_CH0_6 MC_RIR_WAY_CH0_7 MC_RIR_WAY_CH0_8 MC_RIR_WAY_CH0...

Page 7: ...0 MC_THERMAL_STATUS1 MC_THERMAL_STATUS2 92 2 13 3 MC_THERMAL_DEFEATURE0 MC_THERMAL_DEFEATURE1 MC_THERMAL_DEFEATURE2 93 2 13 4 MC_THERMAL_PARAMS_A0 MC_THERMAL_PARAMS_A1 MC_THERMAL_PARAMS_A2 93 2 13 5 M...

Page 8: ...ntegrated Memory Controller Channel 0 Rank Registers 26 2 11 Device 4 Function 3 Integrated Memory Controller Channel 0 Thermal Control Registers 27 2 12 Device 5 Function 0 Integrated Memory Controll...

Page 9: ...eet 9 Revision History Revision Number Description Date 001 Initial release November 2008 002 Updated section 2 2 and Table 2 3 November 2008 003 Updated document title and Introduction chapter Octobe...

Page 10: ...10 Datasheet...

Page 11: ...MB of shared cache and an integrated memory controller The processors support all the existing Streaming SIMD Extensions 2 SSE2 Streaming SIMD Extensions 3 SSE3 and Streaming SIMD Extensions 4 SSE4 T...

Page 12: ...ming model can be found at http developer intel com technology intel64 Intel QuickPath Interconnect A cache coherent link based interconnect specification for Intel processor chipset and I O bridge co...

Page 13: ...s Specification Update http download intel com design processor specup dt 320836 pdf Intel Core i7 900 Desktop Processor Extreme Edition Series and Intel Core i7 900 Desktop Processor Series Datasheet...

Page 14: ...Introduction 14 Datasheet...

Page 15: ...bute can be read and written by software RC Read Clear The bit or bits can be read by software but the act of reading causes the value to be cleared RCW Read Clear Write A register bit with this attri...

Page 16: ...a register that contains a reserved bit is responsible for reading the register modifying the desired bits and writing back the result Reserved Bits Some of the processor registers described in this s...

Page 17: ...ing of Bus Number Device Number and Function Number Device configuration is based on the PCI Type 0 configuration conventions All processor registers appear on the PCI bus assigned for the processor s...

Page 18: ...core Registers DID VID 00h 80h PCISTS PCICMD 04h 84h CCR RID 08h 88h HDR 0Ch 8Ch 10h 90h 14h 94h 18h 98h 1Ch 9Ch 20h A0h 24h A4h 28h A8h SID SVID 2Ch ACh 30h B0h 34h B4h 38h B8h 3Ch BCh 40h C0h 44h C4...

Page 19: ...h SAD_DRAM_RULE_6 98h 1Ch SAD_DRAM_RULE_7 9Ch 20h A0h 24h A4h 28h A8h SID SVID 2Ch ACh 30h B0h 34h B4h 38h B8h 3Ch BCh SAD_PAM0123 40h SAD_INTERLEAVE_LIST_0 C0h SAD_PAM456 44h SAD_INTERLEAVE_LIST_1 C4...

Page 20: ...80h PCISTS PCICMD 04h 84h CCR RID 08h 88h HDR 0Ch 8Ch 10h 90h 14h 94h 18h 98h 1Ch 9Ch 20h A0h 24h A4h 28h A8h SID SVID 2Ch ACh 30h B0h 34h B4h 38h B8h 3Ch BCh 40h C0h 44h C4h QPI_QPILCL_L0 48h C8h 4C...

Page 21: ...D VID 00h 80h PCISTS PCICMD 04h 84h CCR RID 08h 88h HDR 0Ch 8Ch 10h 90h 14h 94h 18h 98h 1Ch 9Ch 20h A0h 24h A4h 28h A8h SID SVID 2Ch ACh 30h B0h 34h B4h 38h B8h 3Ch BCh 40h C0h 44h C4h 48h C8h 4Ch CCh...

Page 22: ...h 1Ch 9Ch 20h A0h 24h A4h 28h A8h SID SVID 2Ch ACh 30h B0h 34h B4h 38h B8h 3Ch BCh 40h C0h 44h C4h MC_CONTROL 48h C8h MC_STATUS 4Ch CCh MC_SMI_SPARE_DIMM_ERROR_STATUS 50h D0h MC_SMI_SPARE_CNTRL 54h D4...

Page 23: ...14h TAD_DRAM_RULE_5 94h 18h TAD_DRAM_RULE_6 98h 1Ch TAD_DRAM_RULE_7 9Ch 20h A0h 24h A4h 28h A8h SID SVID 2Ch ACh 30h B0h 34h B4h 38h B8h 3Ch BCh 40h TAD_INTERLEAVE_LIST_0 C0h 44h TAD_INTERLEAVE_LIST_...

Page 24: ...RAMS B4h 38h MC_CHANNEL_0_SCHEDULER_PARAMS B8h 3Ch MC_CHANNEL_0_MAINTENANCE_OPS BCh 40h MC_CHANNEL_0_TX_BG_SETTINGS C0h 44h C4h 48h MC_CHANNEL_0_RX_BGF_SETTINGS C8h 4Ch MC_CHANNEL_0_EW_BGF_SETTINGS CC...

Page 25: ...84h CCR RID 08h MC_SAG_CH0_2 88h HDR 0Ch MC_SAG_CH0_3 8Ch 10h MC_SAG_CH0_4 90h 14h MC_SAG_CH0_5 94h 18h MC_SAG_CH0_6 98h 1Ch MC_SAG_CH0_7 9Ch 20h A0h 24h A4h 28h A8h SID SVID 2Ch ACh 30h B0h 34h B4h 3...

Page 26: ...MC_RIR_WAY_CH0_12 B0h 34h MC_RIR_WAY_CH0_13 B4h 38h MC_RIR_WAY_CH0_14 B8h 3Ch MC_RIR_WAY_CH0_15 BCh MC_RIR_LIMIT_CH0_0 40h MC_RIR_WAY_CH0_16 C0h MC_RIR_LIMIT_CH0_1 44h MC_RIR_WAY_CH0_17 C4h MC_RIR_LIM...

Page 27: ...OFFSET0 88h HDR 0Ch 8Ch 10h 90h 14h 94h 18h MC_RANK_VIRTUAL_TEMP0 98h 1Ch MC_DDR_THERM_COMMAND0 9Ch 20h A0h 24h MC_DDR_THERM_STATUS0 A4h 28h A8h SID SVID 2Ch ACh 30h B0h 34h B4h 38h B8h 3Ch BCh 40h C0...

Page 28: ...ARAMS B4h 38h MC_CHANNEL_1_SCHEDULER_PARAMS B8h 3Ch MC_CHANNEL_1_MAINTENANCE_OPS BCh 40h MC_CHANNEL_1_TX_BG_SETTINGS C0h 44h C4h 48h MC_CHANNEL_1_RX_BGF_SETTINGS C8h 4Ch MC_CHANNEL_1_EW_BGF_SETTINGS C...

Page 29: ...84h CCR RID 08h MC_SAG_CH1_2 88h HDR 0Ch MC_SAG_CH1_3 8Ch 10h MC_SAG_CH1_4 90h 14h MC_SAG_CH1_5 94h 18h MC_SAG_CH1_6 98h 1Ch MC_SAG_CH1_7 9Ch 20h A0h 24h A4h 28h A8h SID SVID 2Ch ACh 30h B0h 34h B4h 3...

Page 30: ...MC_RIR_WAY_CH1_12 B0h 34h MC_RIR_WAY_CH1_13 B4h 38h MC_RIR_WAY_CH1_14 B8h 3Ch MC_RIR_WAY_CH1_15 BCh MC_RIR_LIMIT_CH1_0 40h MC_RIR_WAY_CH1_16 C0h MC_RIR_LIMIT_CH1_1 44h MC_RIR_WAY_CH1_17 C4h MC_RIR_LIM...

Page 31: ...OFFSET1 88h HDR 0Ch 8Ch 10h 90h 14h 94h 18h MC_RANK_VIRTUAL_TEMP1 98h 1Ch MC_DDR_THERM_COMMAND1 9Ch 20h A0h 24h MC_DDR_THERM_STATUS1 A4h 28h A8h SID SVID 2Ch ACh 30h B0h 34h B4h 38h B8h 3Ch BCh 40h C0...

Page 32: ...ARAMS B4h 38h MC_CHANNEL_2_SCHEDULER_PARAMS B8h 3Ch MC_CHANNEL_2_MAINTENANCE_OPS BCh 40h MC_CHANNEL_2_TX_BG_SETTINGS C0h 44h C4h 48h MC_CHANNEL_2_RX_BGF_SETTINGS C8h 4Ch MC_CHANNEL_2_EW_BGF_SETTINGS C...

Page 33: ...84h CCR RID 08h MC_SAG_CH2_2 88h HDR 0Ch MC_SAG_CH2_3 8Ch 10h MC_SAG_CH2_4 90h 14h MC_SAG_CH2_5 94h 18h MC_SAG_CH2_6 98h 1Ch MC_SAG_CH2_7 9Ch 20h A0h 24h A4h 28h A8h SID SVID 2Ch ACh 30h B0h 34h B4h 3...

Page 34: ...MC_RIR_WAY_CH2_12 B0h 34h MC_RIR_WAY_CH2_13 B4h 38h MC_RIR_WAY_CH2_14 B8h 3Ch MC_RIR_WAY_CH2_15 BCh MC_RIR_LIMIT_CH2_0 40h MC_RIR_WAY_CH2_16 C0h MC_RIR_LIMIT_CH2_1 44h MC_RIR_WAY_CH2_17 C4h MC_RIR_LIM...

Page 35: ...OFFSET2 88h HDR 0Ch 8Ch 10h 90h 14h 94h 18h MC_RANK_VIRTUAL_TEMP2 98h 1Ch MC_DDR_THERM_COMMAND2 9Ch 20h A0h 24h MC_DDR_THERM_STATUS2 A4h 28h A8h SID SVID 2Ch ACh 30h B0h 34h B4h 38h B8h 3Ch BCh 40h C0...

Page 36: ...16 bit register combined with the Vendor Identification register uniquely identifies the Function within the processor Writes to this register have no effect See Table 2 1 for the DID of each process...

Page 37: ...Edition Series and Intel Core i7 900 Desktop Processor Series Specification Update for the value of the Revision ID Register Device 0 Function 0 1 Offset 09h Device 2 Function 0 1 4 5 Offset 09h Devic...

Page 38: ...her this is a multi function device that may have alternative configuration layouts This bit is hardwired to 1 for devices in the processor 6 0 RO 0 Configuration Layout This field identifies the form...

Page 39: ...dwired to 0 Writes to this bit position have no effect 8 RO 0 SERRE SERR Message Enable This bit is a global enable bit for this devices SERR messaging This host bridge will not implement SERR messagi...

Page 40: ...ed to 0 and is read only 12 RO 0 Received Target Abort Status RTAS This bit is set when this device generates a request that receives a Completer Abort completion packet Software clears this bit by wr...

Page 41: ...e state of the interrupt in the device function Only when the Interrupt Disable bit in the command register is a 0 and this Interrupt Status bit is a 1 will the device s function s INTx signal be asse...

Page 42: ...ced by ESI 11 Normal DRAM Operation All reads and writes are serviced by DRAM 13 12 RW 0 PAM1_HIENABLE 0C4000h 0C7FFFh Attribute HIENABLE This field controls the steering of read and write cycles that...

Page 43: ...Only All reads are sent to DRAM All writes are forwarded to ESI 10 Write Only All writes are send to DRAM Reads are serviced by ESI 11 Normal DRAM Operation All reads and writes are serviced by DRAM 9...

Page 44: ...d D_CLS 1 are not set at the same time 12 RW1S 0 SMM Space Locked D_LCK When D_LCK is set to 1 then D_OPEN is reset to 0 and D_LCK D_OPEN C_BASE_SEG G_SMRAME PCIEXBAR DRAM_RULEs and INTERLEAVE_LISTs b...

Page 45: ...Access as a Qword Bit Type Reset Value Description 39 20 RW 0 ADDRESS Base address of PCIEXBAR Must be naturally aligned to size low order bits are ignored 3 1 RW 0 SIZE Size of the PCIEXBAR address...

Page 46: ...ich package the DRAM belongs to This mode selects how that number is computed 00 Address bits 8 7 6 01 Address bits 8 7 6 XORed with 18 17 16 10 Address bit 6 MOD3 Address 39 6 Note 6 is the high orde...

Page 47: ...the corresponding request 20 RW 0 L1_ENABLE Enables L1 mode at the transmitter This bit should be ANDed with the receive L1 capability bit received during parameter exchange to determine if a transmit...

Page 48: ...peline for all other transactions The SAG registers must be appropriately programmed as well 5 RW 0 CHANNELRESET2 Reset only the state within the channel Equivalent to pulling warm reset for that chan...

Page 49: ...written without the channel_active being set Clocks in the channel will be disabled when this bit is set 1 RO 0 CHANNEL1_DISABLED Channel 1 is disabled This can be factory configured or if Init done...

Page 50: ...e channel Bit 0 DIMM 0 Channel 0 Bit 1 DIMM 1 Channel 0 Bit 2 DIMM 2 Channel 0 Bit 3 DIMM 3 Channel 0 Bit 4 DIMM 0 Channel 1 Bit 5 DIMM 1 Channel 1 Bit 6 DIMM 2 Channel 1 Bit 7 DIMM 3 Channel 1 Bit 8...

Page 51: ...This bit functions the same way in Mirror and Independent Modes The possible SMI events enabled by this bit are Any one of the error counters MC_COR_ECC_CNT_X meets the value of SMI_ERROR_THRESHOLD f...

Page 52: ...l 2 to physical channel for Writes 001 Maps to physical Channel 0 010 Maps to physical Channel 1 100 Maps to physical Channel 2 11 9 RW 0 RDLCH1 Mapping of Logical Channel 1 to physical channel for Re...

Page 53: ...re programmed Device 3 Function 0 Offset 64h Access as a Dword Bit Type Reset Value Description 10 9 RW 0 MAXNUMCOL Maximum Number of Columns 00 2 10 columns 01 2 11 columns 10 2 12 columns 11 RSVD 8...

Page 54: ...CRDT_RD_HIGH CRDT_RD_CRIT must not exceed 31 CRDT_RD_HIGH value must correspond to the number of high RTIDs reserved at the IOH CRDT_RD_CRIT value must correspond to the number of critical RTIDs rese...

Page 55: ...et MC_Channel_ _WAQ_PARAMS ISOCENTRYTHRESHHOLD equal to 31 CRIT 2 8 10 MC_SCRUBADDR_LO This register contains part of the address of the last patrol scrub request issued When running Memtest the faili...

Page 56: ...scrub issued Can be written to specify the next scrub address with STARTSCRUB in the MC_SCRUB_CONTROL register For writes to the register this field always contains the Rank ID For reads the followin...

Page 57: ...94h 98h 9Ch Access as a Dword Bit Type Reset Value Description 19 6 RW LIMIT DRAM rule top limit address Must be strictly greater than previous rule even if this rule is disabled unless this rule and...

Page 58: ..._RULE mode 00 Logical channel 0 01 Logical channel 1 10 Logical channel 2 11 Reserved 25 24 RW Logical Channel6 Index 110 of the Interleave List Bits determined from the matching TAD_DRAM_RULE mode 00...

Page 59: ...matching TAD_DRAM_RULE mode 00 Logical channel 0 01 Logical channel 1 10 Logical channel 2 11 Reserved 1 0 RW Logical Channel0 Index 000 of the Interleave List Bits determined from the matching TAD_DR...

Page 60: ...zation step will be skipped 12 RW 0 RDDQDQS_MASK When set the Read DQ DQS step will be skipped 11 RW 0 RCVEN_MASK When set the RCVEN step will be skipped 10 WO 0 RESET_FIFOS When set the TX and RX FIF...

Page 61: ...abling address inversion for MRS writes 24 RW 0 THREE_DIMMS_PRESENT Set when channel contains three DIMMs THREE_DIMMS_PRESENT 1 and QUAD_RANK_PRESENT 1 or SINGLE_QUAD_RANK_PRESENT 1 are mutually exclu...

Page 62: ...d has completed This bit is cleared by hardware on command issuance and set once the command is complete 6 RO 0 WR_DQ_DQS_PASS Set after a training command when the Write DQ DQS training step passes T...

Page 63: ...for a precharge command 27 RW 0 ACTIVATE_VALID Indicates current command is for an activate command 26 RW 0 REG_VALID Indicates current command is for a registered DIMM config write Bit is cleared by...

Page 64: ...ction 0 Offset 68h Access as a Dword Bit Type Reset Value Description 3 2 RW 0 INC_ENTERPWRDWN_RATE Powerdown rate will be increased during thermal throttling based on the following configurations 00...

Page 65: ...this reason bit 1 of the RC2 field bit 21 of this register will be controlled by hardware 23 22 and 20 will be driven with the RDIMM register write command for RC2 19 16 RW 0 RC0 The values to write...

Page 66: ...Description 28 26 RW 0 tddWrTRd Minimum delay between a write followed by a read to different DIMMs 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 8 25 23 RW 0 tdrWrTRd Minimum delay between a write f...

Page 67: ...drRdTWr Minimum delay between Read followed by a write to different ranks on the same DIMM 0000 2 0001 3 0010 4 0011 5 0100 6 0101 7 0110 8 0111 9 1000 10 1001 11 1010 12 1011 13 1100 14 10 7 RW 0 tsr...

Page 68: ...000 2 001 3 010 4 011 5 100 6 101 7 110 8 111 9 3 1 RW 0 tdrRdTRd Minimum delay between reads to different ranks on the same DIMM 000 2 001 3 010 4 011 5 100 6 101 7 110 8 111 9 0 RW 0 tsrRdTRd Minimu...

Page 69: ...so spaces the read data by 0 29 DCLKS The value entered is one less than the spacing required i e a spacing of 5 DCLKS between CAS commands or 1 DCLK on the read data requires a setting of 4 15 13 RW...

Page 70: ...um delay between Activate and Precharge commands 3 0 RW 0 tRP Minimum delay between Precharge command and Activate command Device 4 5 6 Function 0 Offset 8Ch Access as a Dword Bit Type Reset Value Des...

Page 71: ...d command Exit Precharge Power Down with DLL frozen to commands not requiring a locked DLL Slow exit precharge powerdown is not supported 20 11 RW 0 tXSDLL Minimum delay between the exit of self refre...

Page 72: ...g which all commands are blocked for an RCOMP update Data RCOMP update is done on the last DCLK of this period Program this field to 31 for all configurations 3 0 RW 0 RCOMP_INTERVAL Duration of inter...

Page 73: ...CE_ODT7 Force ODT for Rank7 to always be asserted 6 RW 0 FORCE_ODT6 Force ODT for Rank6 to always be asserted 5 RW 0 FORCE_ODT5 Force ODT for Rank5 to always be asserted 4 RW 0 FORCE_ODT4 Force ODT fo...

Page 74: ...atterns driven out onto ODT pins when Rank6 is read 15 8 RW 4 ODT_RD5 Bit patterns driven out onto ODT pins when Rank5 is read 7 0 RW 4 ODT_RD4 Bit patterns driven out onto ODT pins when Rank4 is read...

Page 75: ...1 to disable 19 15 RW 31 ISOCEXITTHRESHOLD Write Major Mode ISOC Exit Threshold When the number of writes in the WAQ drops below this threshold the MC will exit write major mode in the presence of a r...

Page 76: ...when CKE transitions with PowerDown entry exit and SelfRefresh exit 11 RW 0 FLOAT_EN When set the address and command lines will float to save power when commands are not being sent out This setting...

Page 77: ...ET VALUE MOD OFFSET MULTIPLE U Final answer for OFFSET MULTIPLE 2 10 27 MC_CHANNEL_0_RX_BGF_SETTINGS MC_CHANNEL_1_RX_BGF_SETTINGS MC_CHANNEL_2_RX_BGF_SETTINGS These are the parameters used to set the...

Page 78: ...or FIFO BGF used to go between different clocking domains These settings provide the gearing necessary to make that clock crossing Device 4 5 6 Function 0 Offset CCh Access as a Dword Bit Type Reset V...

Page 79: ...e page close flag For a less aggressive page close the length of the count interval is increased and vice versa for a more aggressive page close policy Device 4 5 6 Function 0 Offset DCh Access as a D...

Page 80: ...TX_BG_DATA_OFFSET_SETTINGS_CH0 MC_TX_BG_DATA_OFFSET_SETTINGS_CH1 MC_TX_BG_DATA_OFFSET_SETTINGS_CH2 Integrated Memory Controller Channel Bubble Generator Offsets for DATA FIFO Device 4 5 6 Function 0 O...

Page 81: ...s as a Qword Bit Type Reset Value Description 41 RW 0 MASK_DIMM 1 If set ignore DIMM address during address comparison 40 RW 0 MASK_RANK 1 If set ignore RANK address during address comparison 39 RW 0...

Page 82: ...MASK The INJECT_ECC bit must be set to enable error injection Otherwise no error injection will take place even if the criteria programmed in the MC_CHANNEL_X_ADDR_MATCH register is met Device 4 5 6 F...

Page 83: ...ly They will both use the same MATCH settings if both are enabled Note Along with the INJECT_ECC bit set software must generate the memory traffic that matches the address location programmed in the M...

Page 84: ...two DIMMs per channel or 2 if there are three DIMMs per channel DIMM2 DOD rank offset is always 4 as it is only used in three DIMMs per channel case 9 RW 0 DIMMPRESENT DIMM slot is populated 8 7 RW 0...

Page 85: ...if there are three DIMMs per channel DIMM2 DOD rank offset is always 4 as it is only used in three DIMMs per channel case 9 RW 0 DIMMPRESENT DIMM slot is populated 8 7 RW 0 NUMBANK Defines the number...

Page 86: ...DIMMs per channel or 2 if there are three DIMMs per channel DIMM2 DOD rank offset is always 4 as it is only used in three DIMMs per channel case 9 RW 0 DIMMPRESENT DIMM slot is populated 8 7 RW 0 NUM...

Page 87: ...15 6 SystemAddress 15 6 If Removed 2 bit 8 removed If Removed 1 bit 7 removed If Removed 0 bit 6 removed MemoryAddress 36 6 m 36 6 The following table summarizes the combinations of removed bits and...

Page 88: ...C_RIR_LIMIT_CH2_0 MC_RIR_LIMIT_CH2_1 MC_RIR_LIMIT_CH2_2 MC_RIR_LIMIT_CH2_3 MC_RIR_LIMIT_CH2_4 MC_RIR_LIMIT_CH2_5 MC_RIR_LIMIT_CH2_6 MC_RIR_LIMIT_CH2_7 Channel Rank Limit Range Registers Device 4 Funct...

Page 89: ...CH chan 0 RIR_WAY_CH chan 3 0 RIR_LIMIT_CH chan 1 RIR_WAY_CH chan 7 6 RIR_LIMIT_CH chan 2 RIR_WAY_CH chan 11 10 RIR_LIMIT_CH chan 3 RIR_WAY_CH chan 15 14 RIR_LIMIT_CH chan 4 RIR_WAY_CH chan 19 18 RIR_...

Page 90: ...CH chan 0 RIR_WAY_CH chan 3 0 RIR_LIMIT_CH chan 1 RIR_WAY_CH chan 7 6 RIR_LIMIT_CH chan 2 RIR_WAY_CH chan 11 10 RIR_LIMIT_CH chan 3 RIR_WAY_CH chan 15 14 RIR_LIMIT_CH chan 4 RIR_WAY_CH chan 19 18 RIR_...

Page 91: ...CH chan 0 RIR_WAY_CH chan 3 0 RIR_LIMIT_CH chan 1 RIR_WAY_CH chan 7 6 RIR_LIMIT_CH chan 2 RIR_WAY_CH chan 11 10 RIR_LIMIT_CH chan 3 RIR_WAY_CH chan 15 14 RIR_LIMIT_CH chan 4 RIR_WAY_CH chan 19 18 RIR_...

Page 92: ...RAMS_B SAFE_INTERVAL is exceeded 1 0 RW 0 THROTTLE_MODE S elects throttling mode 00 Throttle disabled 01 Open Loop Throttle when Virtual Temperature is greater than MC_THROTTLE_OFFSET 10 Closed Loop T...

Page 93: ...it Type Reset Value Description 0 RW1S 0 THERM_REG_LOCK When set no further modification of all thermal throttle registers are allowed This bit must be set to the same value for all channels Device 4...

Page 94: ...C_COOLING_COEF or MC_CLOSED_LOOP registers have been written A register to write to MC_COOLING_COEF or MC_CLOSED_LOOP will re apply the normal MC_COOLING_COEF and MC_CLOSED_LOOP MIN_THROTTLE_DUTY_CYC...

Page 95: ...ttle logic is shared Device 4 5 6 Function 3 Offset 84h Access as a Dword Bit Type Reset Value Description 17 8 RW 64 MIN_THROTTLE_DUTY_CYC This parameter represents the minimum number of DCLKs of ope...

Page 96: ...ogic is shared 2 13 10 MC_DDR_THERM_COMMAND0 MC_DDR_THERM_COMMAND1 MC_DDR_THERM_COMMAND2 This register contains the command portion of the DDR_THERM functionality as described in the processor datashe...

Page 97: ...ion 2 RO 0 ASSERTION An assertion edge was seen on DDR_THERM Write 1 to clear 1 RO 0 DEASSERTION A de assertion edge was seen on DDR_THERM Write 1 to clear 0 RO 0 STATE Present logical state of DDR_TH...

Page 98: ...DIMM clock ratio Qclk This is the data rate going to the DIMM The clock sent to the DIMM is 1 2 of QCLK rate Device 3 Function 4 Offset 54h Access as a Dword Bit Type Reset Value Description 4 0 RW 6...

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