Intel BX80623I32100, Datasheet

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Introduction
12 Datasheet, Volume 1
• Up to 64 simultaneous open pages, 32 per channel (assuming 8 ranks of 8 bank
devices)
• Command launch modes of 1n/2n
• On-Die Termination (ODT)
• Asynchronous ODT
• Intel
®
Fast Memory Access (Intel
®
FMA)
— Just-in-Time Command Scheduling
— Command Overlap
— Out-of-Order Scheduling
1.2.2 PCI Express*
• PCI Express* port(s) are fully-compliant with the PCI Express Base Specification,
Revision 2.0 .
• Processor with desktop PCH supported configurations
• The port may negotiate down to narrower widths
— Support for x16/x8/x4/x1 widths for a single PCI Express mode
• 2.5 GT/s and 5.0 GT/s PCI Express* frequencies are supported
• Gen1 Raw bit-rate on the data pins of 2.5 GT/s, resulting in a real bandwidth per
pair of 250 MB/s given the 8b/10b encoding used to transmit data across this
interface. This also does not account for packet overhead and link maintenance.
• Maximum theoretical bandwidth on the interface of 4 GB/s in each direction
simultaneously, for an aggregate of 8 GB/s when x16 Gen 1
• Gen 2 Raw bit-rate on the data pins of 5.0 GT/s, resulting in a real bandwidth per
pair of 500 MB/s given the 8b/10b encoding used to transmit data across this
interface. This also does not account for packet overhead and link maintenance.
• Maximum theoretical bandwidth on the interface of 8 GB/s in each direction
simultaneously, for an aggregate of 16 GB/s when x16 Gen 2
• Hierarchical PCI-compliant configuration mechanism for downstream devices
• Traditional PCI style traffic (asynchronous snooped, PCI ordering)
• PCI Express* extended configuration space. The first 256 bytes of configuration
space aliases directly to the PCI Compatibility configuration space. The remaining
portion of the fixed 4-KB block of memory-mapped space above that (starting at
100h) is known as extended configuration space.
• PCI Express* Enhanced Access Mechanism; accessing the device configuration
space in a flat memory mapped fashion
• Automatic discovery, negotiation, and training of link out of reset
• Traditional AGP style traffic (asynchronous non-snooped, PCI-X Relaxed ordering)
• Peer segment destination posted write traffic (no peer-to-peer read traffic) in
Virtual Channel 0
— DMI -> PCI Express* Port 0
Table 1-1. PCI Express* Supported Configurations in Desktop Products
Configuration Organization Desktop
1 2x8 Graphics, I/O
2 1x16 Graphics, I/O