Intel BX80623I32100 Datasheet Download Page 10 | Manualshive

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Introduction

10

Datasheet, Volume 1

Figure 1-1. Desktop Platform System Block Diagram Example

Intel® Flexible

Display

Interface

DMI2 x4

Discrete Graphics

(PEG)

Analog CRT

Gigabit

Network Connection

USB 2.0

Intel® HD Audio

FWH

Super I/O

Serial ATA

DDR3

PCI Express* 2.0

1 x16 or 2x8

8 PCI Express* 2.0 x1

Ports

(5 GT/s)

SPI

Digital Display x 3

PCI Express*

SPI Flash x 2

LPC

SMBUS 2.0

GPIO

LVDS Flat Panel

WiFi / WiMax

Controller Link 1

Processor

PECI

Platform

Controller

Hub (PCH)

Intel®

Management

Engine

PCI

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Summary of Contents for BX80623I32100

Page 1: ...Processor Family Desktop and Intel Celeron Processor Family Desktop Datasheet Volume 1 Supporting Intel Core i7 i5 and i3 Desktop Processor Series Supporting Intel Pentium Processor G800 and G600 Ser...

Page 2: ...ardware and software configurations and may require a BIOS update Software applications may not be compatible with all operating systems Please check with your application vendor Intel Active Manageme...

Page 3: ...pport 21 2 1 3 System Memory Organization Modes 21 2 1 3 1 Single Channel Mode 21 2 1 3 2 Dual Channel Mode Intel Flex Memory Technology Mode 21 2 1 4 Rules for Populating Memory Slots 22 2 1 5 Techno...

Page 4: ...tures Not Supported 37 3 2 Intel Trusted Execution Technology Intel TXT 38 3 3 Intel Hyper Threading Technology Intel HT Technology 38 3 4 Intel Turbo Boost Technology 39 3 4 1 Intel Turbo Boost Techn...

Page 5: ...ry Reference and Compensation Signals 63 6 3 Reset and Miscellaneous Signals 64 6 4 PCI Express Based Interface Signals 65 6 5 Intel Flexible Display Interface Intel FDI Signals 65 6 6 Direct Media In...

Page 6: ...p Top View Lower Right Quadrant 93 Tables 1 1 PCI Express Supported Configurations in Desktop Products 12 1 2 Terminology 16 1 3 Related Documents 18 2 1 Supported UDIMM Module Configurations 20 2 2 S...

Page 7: ...e Condition Ratings 79 7 5 Processor Core Active and Idle Mode DC Voltage and Current Specifications 80 7 6 Processor System Agent I O Buffer Supply DC Voltage and Current Specifications 82 7 7 Proces...

Page 8: ...and i3 2120T processors Added Intel Celeron processor family desktop Intel Celeron G540 G530 G530T and G440 processors Added Intel Pentium G860 G630 and G630T processors September 2011 004 Added Inte...

Page 9: ...respective platform Note Throughout this document 2nd Generation Intel Core processor family desktop Intel Pentium processor family desktop and Intel Celeron processor family desktop may be referred t...

Page 10: ...ics PEG Analog CRT Gigabit Network Connection USB 2 0 Intel HD Audio FWH Super I O Serial ATA DDR3 PCI Express 2 0 1 x16 or 2x8 8 PCI Express 2 0 x1 Ports 5 GT s SPI Digital Display x 3 PCI Express SP...

Page 11: ...Advanced Vector Extensions Intel AVX Intel Advanced Encryption Standard New Instructions Intel AES NI PCLMULQDQ Instruction 1 2 Interfaces 1 2 1 System Memory Support Two channels of unbuffered DDR3...

Page 12: ...g in a real bandwidth per pair of 500 MB s given the 8b 10b encoding used to transmit data across this interface This also does not account for packet overhead and link maintenance Maximum theoretical...

Page 13: ...sed to transmit data across this interface Does not account for packet overhead and link maintenance Maximum theoretical bandwidth on interface of 2 GB s in each direction simultaneously for an aggreg...

Page 14: ...n DXVA support for accelerating video processing Full AVC VC1 MPEG2 HW Decode Advanced Scheduler 2 0 1 0 XPDM support Windows 7 XP Windows Vista OSX Linux OS Support DX10 1 DX10 DX9 support OGL 3 0 su...

Page 15: ...Express L0s and L1 ASPM power management capability 1 3 5 Direct Media Interface DMI L0s and L1 ASPM power management capability 1 3 6 Processor Graphics Controller Intel Rapid Memory Power Management...

Page 16: ...verrun vulnerabilities and can thus help improve the overall security of the system See the Intel 64 and IA 32 Architectures Software Developer s Manuals for more detailed information IMC Integrated M...

Page 17: ...nterrupt Used in ACPI protocol Storage Conditions A non operational state The processor may be installed in a platform in a tray or loose Processors may be sealed in packaging or exposed to free air U...

Page 18: ...Series Chipset and Intel C200 Series Chipset Datasheet www intel com Assets PDF datas heet 324645 pdf Intel 6 Series Chipset and Intel C200 Series Chipset Thermal Mechanical Specifications and Design...

Page 19: ...d x16 unbuffered non ECC Raw Card B Single Ranked x8 unbuffered non ECC Raw Card C Single Ranked x16 unbuffered non ECC Raw Card F Dual Ranked x8 planar unbuffered non ECC Desktop PCH platform DDR3 DI...

Page 20: ...b 128 M X 16 8 2 14 10 8 16 K B 2 GB 1 Gb 128 M X 8 16 2 14 10 8 8 K 4 GB 2 Gb 256 M X 8 16 2 15 10 8 8 K 8 GB 4 Gb 512 M X 8 16 2 16 10 8 8 K C 512 MB 1 Gb 64 M X 16 4 1 13 10 8 16 K 1 GB 2 Gb 128 M...

Page 21: ...hannel Mode In this mode all memory cycles are directed to a single channel Single channel mode is used when either Channel A or Channel B DIMM connectors are populated in any order but not both 2 1 3...

Page 22: ...vice technology and width may vary from one channel to the other 2 1 4 Rules for Populating Memory Slots In all modes the frequency of system memory is the lowest frequency of all memory modules place...

Page 23: ...n be issued in an overlapping manner increasing the efficiency of system memory protocol 2 1 5 3 Out of Order Scheduling While leveraging the Just in Time Scheduling and Command Overlap enhancements t...

Page 24: ...ions would imply 300 MB s The external graphics ports support Gen2 speed as well At 5 0 GT s Gen 2 operation results in twice as much bandwidth per lane as compared to Gen 1 operation When operating w...

Page 25: ...and applies data protection code and TLP sequence number and submits them to Physical Layer for transmission across the Link The receiving Data Link Layer is responsible for checking the integrity of...

Page 26: ...hanism section The PCI Express Host Bridge is required to translate the memory mapped PCI Express configuration space accesses from the host processor to PCI Express configuration cycles To maintain c...

Page 27: ...PCI INT or GPE Any DMI related SERR activity is associated with Device 0 2 3 2 Processor PCH Compatibility Assumptions The processor is compatible with the Intel 6 Series Chipset PCH The processor is...

Page 28: ...ics Controller GT New Graphics Engine Architecture includes 3D compute elements Multi format hardware assisted decode encode Pipeline and Mid Level Cache MLC for superior high definition playback vide...

Page 29: ...vertex reference received from the VF unit in the order received 2 4 1 2 3 Geometry Shader GS Stage The GS stage receives inputs from the VS stage Compiled application provided GS programs specifying...

Page 30: ...128 bit BLT engine provides hardware acceleration of block transfers of pixel data for many common Windows operations The BLT engine can be used for the following Move rectangular blocks of data betw...

Page 31: ...e associated with Pipes A and B respectively The two display pipes are independent allowing for support of two independent display streams They are both double buffered which minimizes latency and imp...

Page 32: ...y Interface Intel FDI The Intel Flexible Display Interface Intel FDI is a proprietary link for carrying display traffic from the Processor Graphics controller to the PCH display I Os Intel FDI support...

Page 33: ...er The processor implements a PECI interface to Allow communication of processor thermal and other information to the PECI master Read averaged Digital Thermal Sensor DTS values for fan speed control...

Page 34: ...Interfaces 34 Datasheet Volume 1...

Page 35: ...specifications and functional descriptions are included in the Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3B and is available at http www intel com products processor manuals...

Page 36: ...le Exiting Descriptor table exiting allows a VMM to protect a guest OS from internal malicious software based attack by preventing relocation of key system data structures like IDT interrupt descripto...

Page 37: ...ctive IOTLB invalidation MSI cycles MemWr to address FEEx_xxxxh not translated Translation faults result in cycle forwarding to VBIOS region byte enables masked for writes Returned data may be bogus f...

Page 38: ...om potential corruption The enhanced platform provides these launch and control interfaces using Safer Mode Extensions SMX The SMX interface includes the following functions Measured Verified launch o...

Page 39: ...han the TDP at the rated frequency To take advantage of the available thermal headroom the active cores can increase their operating frequency To determine the highest performance frequency amongst ac...

Page 40: ...eration and authenticated encryption AES is broadly accepted as the standard for both government and industry applications and is widely deployed in various protocols Intel AES NI consists of six Inte...

Page 41: ...D and a 16 bit logical ID within the cluster Consequently 2 20 16 processors can be addressed in logical destination mode Processor implementations can support fewer than 16 bits in the cluster ID sub...

Page 42: ...Technologies 42 Datasheet Volume 1...

Page 43: ...DMI Processor Graphics Controller Figure 4 1 Power States G0 Working S0 CPU Fully powered on C0 Active mode C1 Auto halt C1E Auto halt low freq low voltage C3 L1 L2 caches flush clocks off C6 save co...

Page 44: ...e processor executing code C1 AutoHALT state C1E AutoHALT state with lowest frequency and voltage operating point C3 Execution cores in C3 flush their L1 instruction cache L1 data cache and L2 cache t...

Page 45: ...tate power off Longest exit latency Table 4 6 Processor Graphics Controller States State Description D0 Full on display active D3 Cold Power off Table 4 7 G S and C State Combinations Global G State S...

Page 46: ...established the PLL locks on to the target frequency If the target frequency is lower than the current frequency the PLL locks to the target frequency then transitions to a lower voltage by signaling...

Page 47: ...ate Note 1 If enabled the core C state will be C1E if all enabled cores have also resolved a core C1 state or higher Figure 4 2 Idle Power Management Breakdown of the Processor Cores Processor Package...

Page 48: ...ctionality Any P_LVLx reads outside of this range does not cause an I O redirection to MWAIT Cx like request They fall through like a normal I O instruction Note When P_LVLx I O instructions are used...

Page 49: ...can enter the C6 state by initiating a P_LVL3 I O read or an MWAIT C6 instruction Before entering core C6 the core will save its architectural state to a dedicated SRAM Once complete a core will have...

Page 50: ...g any other C state The processor exits a package C state when a break event is detected Depending on the type of break event the processor does the following If a core break event is received the tar...

Page 51: ...rocessor automatically transitions to the lowest supported core clock frequency followed by a reduction in voltage The package enters the C1 low power state when At least one core is in the C1 state T...

Page 52: ...L3 cache is active 4 3 Integrated Memory Controller IMC Power Management The main memory is power managed during normal operation and in low power ACPI Cx states 4 3 1 Disabling Unused System Memory O...

Page 53: ...modes Power consumption is defined by IDD2P1 Exiting this mode is defined by tXP but also tXPDLL 10 20 according to DDR type cycles until first data transfer is allowed The processor supports 5 diffe...

Page 54: ...e timer Another option associated with CKE power down is the S_DLL off When this option is enabled the SBR I O slave DLLs go off when all channel ranks are in power down Do not confuse it with the DLL...

Page 55: ...signals should be disabled to save power and reduce electromagnetic interference This includes all signals associated with an unused memory channel Clocks can be controlled on a per SO DIMM basis Exce...

Page 56: ...intained by Intel Graphics Dynamic Frequency also known as Turbo Boost Technology 4 6 3 Graphics Render C State Render C State RC6 is a technique designed to optimize the average power to the graphics...

Page 57: ...ase application performance The increase in frequency is determined by how much power and thermal budget is available in the package and the application demand for additional processor or graphics per...

Page 58: ...Power Management 58 Datasheet Volume 1...

Page 59: ...ermal specifications and design guidelines refer to the 2nd Generation Intel Core Processor Family Desktop Intel Pentium Processor Family Desktop and Intel Celeron Processor Family Desktop and LGA1155...

Page 60: ...Thermal Management 60 Datasheet Volume 1...

Page 61: ...scription Buffer Types Signal Description PCI Express PCI Express interface signals These signals are compatible with PCI Express 2 0 Signalling Environment AC Specifications and are AC coupled The bu...

Page 62: ...its SA_DQS 8 0 during read and write transactions I O DDR3 SA_DQ 63 0 Data Bus Channel A data signal interface to the SDRAM data bus I O DDR3 SA_MA 15 0 Memory Address These signals are used to provid...

Page 63: ...nal interface to the SDRAM data bus I O DDR3 SB_MA 15 0 Memory Address These signals are used to provide the multiplexed row and column address to the SDRAM O DDR3 SB_CK 3 0 SDRAM Differential Clock C...

Page 64: ...on the board for this lane CFG 6 5 PCI Express BifurcationNote1 00 1 x8 2 x4 PCI Express 01 Reserved 10 2 x8 PCI Express 11 1 x16 PCI Express CFG 17 7 Reserved configuration lanes A test point may be...

Page 65: ...X 3 0 1 PCI Express Receive Differential Pair I PCI Express PEG_TX 15 0 PEG_TX 15 0 PE_TX 3 0 1 PE_TX 3 0 1 PCI Express Transmit Differential Pair O PCI Express Table 6 7 Intel Flexible Display Interf...

Page 66: ...lel to the top side debug probe to enable debug capacities I DBR DBR is used only in systems where no debug port is implemented on the system board DBR is used by a debug port interposer so that an in...

Page 67: ...Output THERMTRIP Thermal Trip The processor protects itself from catastrophic overheating by use of an internal thermal sensor This sensor is set well above the normal operating temperature to ensure...

Page 68: ...an isolated low impedance connection to the processor core voltage and ground They can be used to sense or measure voltage near the silicon O Analog VAXG_SENSE VSSAXG_SENSE VAXG_SENSE and VSSAXG_SENSE...

Page 69: ...6 Processor Internal Pull Up Pull Down Resistors Signal Name Pull Up Pull Down Rail Value BPM 7 0 Pull Up VCCIO 65 165 PRDY Pull Up VCCIO 65 165 PREQ Pull Up VCCIO 65 165 TCK Pull Down VSS 5 15 k TDI...

Page 70: ...Signal Description 70 Datasheet Volume 1...

Page 71: ...n power planes to sag below their minimum values if bulk decoupling is not adequate Larger bulk storage CBULK such as electrolytic capacitors supply current during longer lasting changes in current de...

Page 72: ...tion VID The processor uses three signals for the serial voltage identification interface to support automatic selection of voltages Table 7 1 specifies the voltage level corresponding to the eight bi...

Page 73: ...0 0 0 1 9 1 0 97000 0 0 0 1 0 0 1 0 1 2 0 33500 1 0 0 1 0 0 1 0 9 2 0 97500 0 0 0 1 0 0 1 1 1 3 0 34000 1 0 0 1 0 0 1 1 9 3 0 98000 0 0 0 1 0 1 0 0 1 4 0 34500 1 0 0 1 0 1 0 0 9 4 0 98500 0 0 0 1 0 1...

Page 74: ...000 0 1 0 0 0 0 0 0 4 0 0 56500 1 1 0 0 0 0 0 0 C 0 1 20500 0 1 0 0 0 0 0 1 4 1 0 57000 1 1 0 0 0 0 0 1 C 1 1 21000 0 1 0 0 0 0 1 0 4 2 0 57500 1 1 0 0 0 0 1 0 C 2 1 21500 0 1 0 0 0 0 1 1 4 3 0 58000...

Page 75: ...500 1 1 1 0 1 0 1 0 E A 1 41500 0 1 1 0 1 0 1 1 6 B 0 78000 1 1 1 0 1 0 1 1 E B 1 42000 0 1 1 0 1 1 0 0 6 C 0 78500 1 1 1 0 1 1 0 0 E C 1 42500 0 1 1 0 1 1 0 1 6 D 0 79000 1 1 1 0 1 1 0 1 E D 1 43000...

Page 76: ...ay result in component malfunction or incompatibility with future processors See Chapter 8 for a land listing of the processor and the location of all reserved signals For reliable operation always co...

Page 77: ...B_WE SA_MA 15 0 SB_MA 15 0 SA_BS 2 0 SB_BS 2 0 SM_DRAMRST SA_CS 3 0 SB_CS 3 0 SA_ODT 3 0 SB_ODT 3 0 SA_CKE 3 0 SB_CKE 3 0 DDR3 Data Signals2 Single ended DDR3 Bi directional SA_DQ 63 0 SB_DQ 63 0 Diff...

Page 78: ...e of the other components is capable of accepting an input of the appropriate voltage Two copies of each signal may be required with each driving a different voltage level The processor supports Bound...

Page 79: ...n methods may follow JESD22 A119 low temp and JESD22 A103 high temp standards when applicable for volatile memory 5 Intel branded products are specified and certified to meet the following temperature...

Page 80: ...ociated with each parameter 7 10 1 Voltage and Current Specifications Table 7 5 Processor Core Active and Idle Mode DC Voltage and Current Specifications Sheet 1 of 2 Symbol Parameter Min Typ Max Unit...

Page 81: ...specification is based on the VCC loadline at worst case highest tolerance and ripple 5 The VCC specifications represent static and transient limits 6 The loadlines specify voltage limits at the die...

Page 82: ...cifications Symbol Parameter Min Typ Max Unit Note 1 VCCSA Voltage for the system agent 0 879 0 925 0 971 V 2 VDDQ Processor I O supply voltage for DDR3 1 425 1 5 1 575 V VCCPLL PLL supply voltage DC...

Page 83: ...is programmed with a maximum valid voltage identification value VID that is set at manufacturing and cannot be altered Individual maximum VID values are calibrated during manufacturing such that two p...

Page 84: ...9 VIL Input Low Voltage SM_VREF 0 1 V 2 4 VIH Input High Voltage SM_VREF 0 1 V 3 VOL Output Low Voltage VDDQ 2 RON RON RTERM 6 VOH Output High Voltage VDDQ VDDQ 2 RON RON RTERM V 4 6 RON_UP DQ DDR3 d...

Page 85: ...y RLRX CM to 50 20 must be within the specified range by the time Detect is entered 10 Low impedance defined during signaling Parameter is captured for 5 0 GHz by RLTX DIFF 11 These are pre silicon es...

Page 86: ...implemented as analog to digital converters calibrated at the factory PECI provides an interface for external devices to read the DTS temperature for thermal management and fan speed control More det...

Page 87: ...ffers in both client and host models must use a Schmitt triggered input design for improved noise immunity Use Figure 7 2 as a guide for input buffer design Table 7 11 PECI DC Electrical Limits Symbol...

Page 88: ...Electrical Specifications 88 Datasheet Volume 1...

Page 89: ...al Information 8 Processor Pin and Signal Information 8 1 Processor Pin Assignments The processor pinmap quadrants are shown in Figure 8 1 through Figure 8 4 Table 8 1 provides a listing of all proces...

Page 90: ..._DQ 40 SB_DQ 41 VSS SB_DQ 37 SB_DQ 36 VSS SB_ODT 1 VSS SB_RAS SB_BS 0 VSS SB_CK 3 AN SA_DQ 47 SA_DQ 46 SA_DQ 42 SA_DQ 43 VSS VSS VSS VSS VSS VSS VSS SB_DQS 4 SB_DQS 4 VSS SB_CS 1 SB_CS 0 VSS SB_MA 10...

Page 91: ...18 SB_DQ 22 SB_DQS 2 SB_DQ 16 SB_DQ 20 VSS VSS SA_DQS 1 SA_DQS 1 VSS AP RSVD VSS SB_MA 8 VSS SB_DQS 8 SB_DQS 8 VSS SB_DQS 3 SB_DQS 3 VSS VSS VSS VSS VSS VSS VSS SA_DQ 9 SA_DQ 13 SA_DQ 12 SA_DQ 8 AN SB...

Page 92: ...VD VSS PROC_SEL RSVD VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC J U N CO R EPWRG O O D TRST CFG 8 CFG 2 CFG 1 PECI RSVD RSVD VSS RSVD VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC H BPM 0 VSS BPM 1 VSS CFG 0 V...

Page 93: ...12 PEG_RX 12 VSS VSS K VSS VCC VCC VSS VCC VCC PEG_TX 4 PEG_TX 4 VCC VSS VCCSA RSVD VCCIO VCCIO PEG_TX 12 PEG_TX 12 VCCIO VCCIO PEG_RX 11 PEG_RX 11 J VSS VCC VCC VSS VCC VCC VCC VCC VCCSA VCCSA VCCSA...

Page 94: ...4 DMI I DMI_RX 3 AA5 DMI I DMI_TX 0 V7 DMI O DMI_TX 1 W7 DMI O DMI_TX 2 Y6 DMI O DMI_TX 3 AA7 DMI O DMI_TX 0 V6 DMI O DMI_TX 1 W8 DMI O DMI_TX 2 Y7 DMI O DMI_TX 3 AA8 DMI O FC_AH1 AH1 N A O FC_AH4 AH4...

Page 95: ...EG_RX 7 E1 PCI Express I PEG_RX 8 F3 PCI Express I PEG_RX 9 G1 PCI Express I PEG_TX 0 C13 PCI Express O PEG_TX 1 E14 PCI Express O Table 8 1 Processor Pin List by Pin Name Pin Name Pin Buffer Type Dir...

Page 96: ...6 DDR3 O SA_CK 0 AW25 DDR3 O SA_CK 1 AU25 DDR3 O SA_CK 2 AY27 DDR3 O SA_CK 3 AW26 DDR3 O SA_CKE 0 AV19 DDR3 O SA_CKE 1 AT19 DDR3 O SA_CKE 2 AU18 DDR3 O SA_CKE 3 AV18 DDR3 O SA_CS 0 AU29 DDR3 O SA_CS 1...

Page 97: ...1 AP3 DDR3 I O SA_DQS 2 AW4 DDR3 I O SA_DQS 3 AV8 DDR3 I O SA_DQS 4 AV37 DDR3 I O SA_DQS 5 AP38 DDR3 I O Table 8 1 Processor Pin List by Pin Name Pin Name Pin Buffer Type Dir SA_DQS 6 AK38 DDR3 I O SA...

Page 98: ..._DQ 25 AM13 DDR3 I O Table 8 1 Processor Pin List by Pin Name Pin Name Pin Buffer Type Dir SB_DQ 26 AR13 DDR3 I O SB_DQ 27 AP13 DDR3 I O SB_DQ 28 AL12 DDR3 I O SB_DQ 29 AL13 DDR3 I O SB_DQ 30 AR12 DDR...

Page 99: ...26 DDR3 O SB_MA 14 AY16 DDR3 O SB_MA 15 AV16 DDR3 O SB_ODT 0 AL26 DDR3 O SB_ODT 1 AP26 DDR3 O SB_ODT 2 AM26 DDR3 O SB_ODT 3 AK26 DDR3 O SB_RAS AP24 DDR3 O SB_WE AR25 DDR3 O SKTOCC AJ33 Analog O SM_DRA...

Page 100: ...VCC F22 PWR VCC F24 PWR VCC F25 PWR VCC F27 PWR VCC F28 PWR Table 8 1 Processor Pin List by Pin Name Pin Name Pin Buffer Type Dir VCC F30 PWR VCC F31 PWR VCC F32 PWR VCC F33 PWR VCC F34 PWR VCC G15 PW...

Page 101: ...Table 8 1 Processor Pin List by Pin Name Pin Name Pin Buffer Type Dir VCCAXG AB38 PWR VCCAXG AB39 PWR VCCAXG AB40 PWR VCCAXG AC33 PWR VCCAXG AC34 PWR VCCAXG AC35 PWR VCCAXG AC36 PWR VCCAXG AC37 PWR V...

Page 102: ...33 N A O VCCIO_SENSE AB4 Analog O VCCPLL AK11 PWR Table 8 1 Processor Pin List by Pin Name Pin Name Pin Buffer Type Dir VCCPLL AK12 PWR VCCSA H10 PWR VCCSA H11 PWR VCCSA H12 PWR VCCSA J10 PWR VCCSA K1...

Page 103: ...8 GND VSS AJ12 GND VSS AJ15 GND VSS AJ18 GND VSS AJ21 GND Table 8 1 Processor Pin List by Pin Name Pin Name Pin Buffer Type Dir VSS AJ25 GND VSS AJ27 GND VSS AJ36 GND VSS AJ5 GND VSS AK1 GND VSS AK10...

Page 104: ...S AP40 GND VSS AP5 GND VSS AR11 GND VSS AR14 GND VSS AR17 GND Table 8 1 Processor Pin List by Pin Name Pin Name Pin Buffer Type Dir VSS AR18 GND VSS AR19 GND VSS AR27 GND VSS AR30 GND VSS AR36 GND VSS...

Page 105: ...VSS C32 GND VSS C35 GND VSS C7 GND VSS C8 GND VSS D17 GND VSS D2 GND Table 8 1 Processor Pin List by Pin Name Pin Name Pin Buffer Type Dir VSS D20 GND VSS D23 GND VSS D26 GND VSS D29 GND VSS D32 GND...

Page 106: ...GND VSS K6 GND VSS L10 GND VSS L17 GND VSS L20 GND VSS L23 GND Table 8 1 Processor Pin List by Pin Name Pin Name Pin Buffer Type Dir VSS L26 GND VSS L29 GND VSS L8 GND VSS M1 GND VSS M17 GND VSS M2 G...

Page 107: ...7 VSS V5 GND VSS W6 GND VSS Y5 GND VSS Y8 GND VSS_NCTF A4 GND VSS_NCTF AV39 GND VSS_NCTF AY37 GND VSS_NCTF B3 GND VSS_SENSE B36 Analog O VSSAXG_SENSE M32 Analog O VSSIO_SENSE AB3 Analog O Table 8 1 Pr...

Page 108: ...Processor Pin and Signal Information 108 Datasheet Volume 1...

Page 109: ...ill allow a better use of the product across different platforms Swizzling has no effect on functional operation and is invisible to the OS SW However during debug swizzling needs to be taken into con...

Page 110: ...AV9 DQ28 SA_DQ 27 AU9 DQ29 SA_DQ 28 AV7 DQ24 SA_DQ 29 AW7 DQ26 SA_DQ 30 AW9 DQ30 SA_DQ 31 AY9 DQ31 SA_DQ 32 AU35 DQ35 SA_DQ 33 AW37 DQ34 SA_DQ 34 AU39 DQ38 SA_DQ 35 AU36 DQ39 SA_DQ 36 AW35 DQ33 SA_DQ...

Page 111: ...AR13 DQ29 SB_DQ 27 AP13 DQ28 SB_DQ 28 AL12 DQ24 SB_DQ 29 AL13 DQ31 SB_DQ 30 AR12 DQ27 SB_DQ 31 AP12 DQ26 SB_DQ 32 AR28 DQ32 SB_DQ 33 AR29 DQ34 SB_DQ 34 AL28 DQ39 SB_DQ 35 AL29 DQ37 SB_DQ 36 AP28 DQ33...

Page 112: ...DDR Data Swizzling 112 Datasheet Volume 1...

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