Errata
Specification Update
31
Implication:
Due to this erratum, FSB marginality is observed during processor core to
core transactions as well as during read transactions driven by the Memory
Controller Hub (MCH) leading to unpredictable system behavior.
Workaround:
It is possible for BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the
Summary Tables of Changes
.
AA45.
A VM Exit Occuring in IA-32e Mode May Not Produce a VMX Abort
When Expected
Problem:
If a VM exit occurs while the processor is in IA-32e mode and the “host
address-space size” VM-exit control is 0, a VMX abort should occur. Due to
this erratum, the expected VMX aborts may not occur and instead the VM Exit
will occur normally. The conditions required to observe this erratum are a VM
entry that returns from SMM with the “IA-32e guest” VM-entry control set to
1 in the SMM VMCS and the “host address-space size” VM-exit control cleared
to 0 in the executive VMCS.
Implication:
A VM Exit will occur when a VMX Abort was expected.
Workaround:
An SMM VMM should always set the “IA-32e guest” VM-entry control in the
SMM VMCS to be the value that was in the LMA bit (IA32_EFER.LMA.LMA[bit
10]) in the IA32_EFER MSR (C0000080H) at the time of the last SMM VM
exit. If this guideline is followed, that value will be 1 only if the “host
address-space size” VM-exit control is 1 in the executive VMCS.
Status:
For the steppings affected, see the
Summary Tables of Changes
.
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