Errata
16
Specification Update
Errata
AA1.
Bus Locks and SMC Detection May Cause the Processor to Hang
Temporarily
Problem:
The processor may temporarily hang in an Hyper-Threading Technology
enabled system if one logical processor executes a synchronization loop that
includes one or more locks and is waiting for release by the other logical
processor. If the releasing logical processor is executing instructions that are
within the detection range of the self -modifying code (SMC) logic, then the
processor may be locked in the synchronization loop until the arrival of an
interrupt or other event.
Implication:
If this erratum occurs in an HT Technology enabled system, the application
may temporarily stop making forward progress. Intel has not observed this
erratum with any commercially available software.
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Tables of Changes
.
AA2.
Memory Aliasing of Pages As Uncacheable Memory Type and Write Back (WB)
May Hang the System
Problem:
When a page is being accessed as either Uncacheable (UC) or Write
Combining (WC) and WB, under certain bus and memory timing conditions,
the system may loop in a continual sequence of UC fetch, implicit writeback,
and Request For Ownership (RFO) retries.
Implication:
This erratum has not been observed in any commercially available operating
system or application. The aliasing of memory regions, a condition necessary
for this erratum to occur, is documented as being unsupported in the
IA-32
Intel
®
Architecture Software Developer's Manual
, Volume 3
,
section 10.12.4,
Programming the PAT. However, if this erratum occurs the system may hang.
Workaround:
The pages should not be mapped as either UC or WC and WB at the same
time.
Status:
For the stepping affected, see the
Summary Tables of Changes.
