Errata
26
Specification Update
AA30.
During an Enhanced HALT or Enhanced Intel SpeedStep
®
Technology
Ratio Transition the System May Hang
Problem:
The BNR signal may not function properly during an Enhanced HALT or
Enhanced Intel SpeedStep Technology ratio transition.
Implication:
The system may hang due to incorrect BNR signaling.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the
Summary Tables of Changes.
AA31.
L2 Cache ECC Machine Check Errors May be erroneously Reported
after an Asynchronous RESET# Assertion
Problem:
Machine check status MSRs may incorrectly report the following L2 Cache
ECC machine-check errors when cache transactions are in-flight and RESET#
is asserted:
•Instruction Fetch Errors (IA32_MC2_STATUS with MCA error code 153)
•L2 Data Write Errors (IA32_MC1_STATUS with MCA error code 145)
Implication:
Uncorrected or corrected L2 ECC machine check errors may be erroneously
reported. Intel has not observed this erratum on any commercially available
system.
Workaround:
When a real run-time L2 Cache ECC Machine Check occurs, a corresponding
valid error will normally be logged in the IA32_MC0_STATUS register. BIOS
may clear IA32_MC2_STATUS and/or IA32_MC1_STATUS for these specific
errors when IA32_MC0_STATUS does not have its VAL flag set.
Status:
For the steppings affected, see the
Summary Tables of Changes
.
AA32.
VMCALL to Activate Dual-monitor Treatment of SMIs and SMM
Ignores Reserved Bit settings in VM-exit Control Field
Problem:
Processors supporting Intel
®
Virtualization Technology can execute VMCALL
from within the Virtual Machine Monitor (VMM) to activate dual-monitor
treatment of SMIs and SMM. Due to this erratum, if reserved bits are set to
values inconsistent with VMX Capability MSRs, VMCALL may not VMFail.
Implication:
VMCALL executed to activate dual-monitor treatment of SMIs and SMM may
not VMFail due to incorrect reserved bit settings in VM-Exit control field.
Workaround:
Software should ensure that all VMCS reserved bits are set to values
consistent with VMX Capability MSRs.
Status:
For the steppings affected, see the
Summary Tables of Changes.
