Errata
22
Specification Update
AA17.
Power Down Requests May not be Serviced if a Power Down
Transition is Interrupted by an In-Target Probe Event in the Presence
of a Specific Type of VM Exit
Problem:
In a system supporting Intel
®
Virtualization Technology, the processor may
service a pended VM exit prior to completely exiting out of a low power state
when the following sequences of events occur:
•
Chip-wide power down transition occurs and
•
VM exit due to a VMLaunch, VMResume, STI, POPF, POPFD, or IRET instruction is
pended and
•
Chip-wide power down transition is interrupted by an In-Target Probe event.
Implication:
Due to this erratum the processor may not recognize further STPCLK#
assertions, TM1, TM2, or Enhanced Intel SpeedStep
®
technology. Intel has
not observed this erratum with any commercially available software.
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Tables of Changes.
AA18.
VM EXIT Due to TPR shadow Below Threshold May Improperly Set
and Cause "Blocking by STI" actions
Problem:
In a system supporting Intel
®
Virtualization Technology and Intel
®
EM64T,
the “blocking by STI” bit of the interruptibility-state field may be saved as 1
rather than 0. This erratum may occur when a STI instruction is executed
directly prior to a MOV to CR8 which results in a VM exit due to a reduction of
the TPR shadow value below the TPR threshold.
Implication:
When this erratum occurs, delivery of an interrupt may be delayed by one
instruction.
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Tables of Changes.
AA19.
Two Correctable L2 Cache Errors in Close Proximity May Cause a
System Hang
Problem:
If two correctable L2 cache errors are detected in close proximity to each
other, a livelock may occur as a result of the processor being unable to
resolve this condition.
Implication:
When this erratum occurs, the processor may livelock and result in a system
hang. Intel has only observed this erratum while injecting cache errors in
simulation..
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Tables of Changes.
