Errata
20
Specification Update
Implication:
The value in CR2 is correct at the time that an architectural page fault is
signaled. Intel has not observed this erratum with any commercially
available software.
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Tables of Changes
.
AA12.
REP STOS/MOVS Instructions with RCX >=2^32 May Cause a System
Hang
Problem:
In IA-32e mode using Intel EM64T-enabled processors, executing a repeating
string instruction with the iteration count greater than or equal to 2^32 and a
pending event may cause the REP STOS/MOVS instruction to live lock and
hang.
Implication:
When this erratum occurs, the processor may live lock and result in a system
hang. Intel has not observed this erratum with any commercially available
software.
Workaround:
Do not use strings larger than 4 GB.
Status:
For the steppings affected, see the
Summary Tables of Changes
.
AA13.
A 64-Bit Value of Linear Instruction Pointer (LIP) May be Reported
Incorrectly in the Branch Trace Store (BTS) Memory Record or in the
Precise Event Based Sampling (PEBS) Memory Record
Problem:
On a processor supporting Intel
®
EM64T,
•
If an instruction fetch wraps around the 4G boundary in Compatibility Mode, the
64-bit value of LIP in the BTS memory record will be incorrect (upper 32 bits will
be set to FFFFFFFFh when they should be 0).
•
If a PEBS event occurs on an instruction whose last byte is at memory location
FFFFFFFFh, the 64-bit value of LIP in the PEBS record will be incorrect (upper 32
bits will be set to FFFFFFFFh when they should be 0).
Implication:
Intel has not observed this erratum on any commercially available software.
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Tables of Changes
.
