Intel 82801EB, Programmer'S Reference Manual

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Theory of Operation
R
16 SATA Programmer’s Reference Manual
4.1.3 Compatible Configuration - Option 2
This option is selected when one or more (maximum of two) SATA devices are to be used. P-ATA
device(s)
may or may not be attached to the P-ATA channels, but will not be accessible to
software. Figure 2 illustrates this configuration:
Figure 2. Compatible Configuration - Option 2
M
Intel
®
ICH5
P-ATA
S-ATA
Port 1
M
Logical Primary
Port 0
Logical Secondary
BIOS Selectable
S
M
M
S
Di
sabl
ed
Note: In the figure above, devices represented by dotted lines may be attached, but are not accessible to
software.
Note: In this configuration, software reads and writes to the slave device registers will result in a master
abort and as such reading from the slave device registers will return all 1. The Drive/Head register
(offset 06h in the command block) is the exception.
To enable this configuration, system BIOS:
1. Shall not program the P-ATA (Device 31, Function 1) controller’s base address registers
(Offsets 10h – 24h in PCI configuration space).
2. Shall disable access to the P-ATA controller’s I/O space by programming the command
register (PCI configuration, offset 04h, bit 0) with a 0.
3. Shall disable the P-ATA function by programming bit 1 ( D31_ F1_DISABLE ) of the
Function Disable register (Device 31, Function 0, Offset F2h) with a 1. This will insure that
the PCI configuration registers associated with the P-ATA function are not decoded and thus
will insure that operating system configuration software does not enumerate and configure the
P-ATA function.
4. Shall program the MAP.MV register as follows:
Note: These mappings represent a master-master device arrangement.