Intel 82801EB, Programmer'S Reference Manual

Page: 35 / 59

Theory of Operation
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SATA Programmer’s Reference Manual 35
// depending on which port is configured as primary and secondary
Device( DRV0) // Logical primary master
{
Name( _ADR, 0)
…
}
//
// Handle transitions to D0 power state
//
Method(_PS0,0)
{
//
// make sure the OS drivers finds the ports in an enabled state as they
// (the device drivers) may have been designed for P-ATA and ‘know’
// nothing about the PCS register
//
// Since enhance mode implements a master-master scheme, only 1 port
// would be enabled here (dependent on the MAP settings). In Combined
// mode, both SATA ports are viewed as a single logical channel
// implementing a master-slave configuration in which case both ports are
// enabled.
//
//
// Enable Power to the device - Set the GPIO(s) bit corresponding to the
// power plane control. This shall be done before
// the port(s) are enabled. This is platform specific
//
… // power plane control is platform specific
// Must wait 30ms before we can enable the ports
Sleep( 30)
EPRT( 0x03) // enable the ports – assumes combined mode
//
// Check ports and disable device power plane if port(s) not enabled.
//
… // power plane control is platform specific
}
//
// Handle transitions to D3 power state
//
Method(_PS3,0)
{
//
// Disable the ports. Since a non-SATA aware driver could be in use,