Intel 82801EB, Programmer'S Reference Manual

Page: 18 / 59

Theory of Operation
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18 SATA Programmer’s Reference Manual
To enable this configuration, the system BIOS:
1. Shall not program the P-ATA (Device 31, Function 1) controller’s base address registers
(Offsets 10h – 24h in PCI configuration space).
2. Shall disable access to the P-ATA controller’s I/O space by programming the command
register (PCI configuration, offset 04h, bit 0) with a 0.
3. Shall disable the P-ATA function by programming bit 1 ( D31_ F1_DISABLE ) of the Function
Disable register (Device 31, Function 0, Offset F2h) with a 1. This will insure that the PCI
configuration registers associated with the P-ATA function are not decoded and thus will
insure that operating system configuration software does not enumerate and configure the P-
ATA function.
4. Shall program the MAP.MV register as follows:
•
If SATA is the primary channel and P-ATA is the secondary channel and Port 0 device is
primary master and Port 1 device is primary slave then MAP.MV == ‘100b’. Figure 4
illustrates this configuration:
Figure 4. Compatible Configuration - Option 3a
S-ATA
P-ATA
Port 0
Port 1
M
S
Logical Primary
Channel
Intel® ICH5
M
S
Physical Primary
Channel
Not Used
M
S
Logical Secondary
Channel
Note: In the figure above, devices represented by dotted lines may be attached, but are not accessible to
software.
•
If SATA is the primary channel and P-ATA is the secondary channel and Port 0 device is
primary slave and Port 1 device is primary master then MAP.MV == ‘101b’. Figure 5
illustrates this configuration: