Inrevium TB-KU-060/075-ACDC8K, Hardware User Manual

Page: 82 / 89

TB-KU-xxx-ACDC8K Hardware User Manual
82
Rev. 1.03
Table 7-16 SPI Flash Memory Pin Assignment
Signal Name FPGA Bank
FPGA
Pin
Primary Flash
SPIFLASH_HR_1_CS_N 0 AB9
SPIFLASH_HR_1_IO_0 0 AE11
SPIFLASH_HR_1_IO_1 0 AD10
SPIFLASH_HR_1_IO_2 0 AC9
SPIFLASH_HR_1_IO_3 0 AD9
CLK_FPGA_CCLK 0 AC11
Secondary Flash
SPIFLASH_HR_2_CS_N 65 AW16
SPIFLASH_HR_2_IO_0 65 AF14
SPIFLASH_HR_2_IO_1 65 AG14
SPIFLASH_HR_2_IO_2 65 AE13
SPIFLASH_HR_2_IO_3 65 AF13
CLK_FPGA_CCLK 0 AC11
Xilinx Core User IO
SPIFLASH_ZYNQ_CS_N 47 P29
SPIFLASH_ZYNQ_IO_0 47 N29
SPIFLASH_ZYNQ_IO_1 47 L32
SPIFLASH_ZYNQ_IO_2 47 L33
SPIFLASH_ZYNQ_IO_3 47 R30
SPIFLASH_ZYNQ_CFG_OD 65 AV16
CLK_ZYNQ_CONFIG_CCLK 47 P30
7.10. JTAG and Pmod Interface
7.10.1. JTAG Connector
The TB-KU-xxx-ACDC8K provides a JTAG interface that follows the Xilinx 14-pin JTAG standard.
Table 7-17 Xilinx 14-pin JTAG Pinout
Pin Xilinx 14-pin JTAG Pin
1 GND VREF 2
3 GND TMS 4
5 GND TCK 6
7 GND TDO 8
9 GND TDI 10
11 GND NC 12
13 GND NC 14
Table 7-18 FPGA Bank 0 JTAG Pin Assignment
Signal Name TMS TCK TDO TDI
FPGA Bank 0 Pin W11 AA11 T10 U11