TB-KU-xxx-ACDC8K Hardware User Manual
33
Rev. 1.03
For FMC 0 (J1):
*1: There are no GTH channels on this connector so the GBTCLK1_M2C_P/N signals are not
connected.
*2: SCL, SDA
The board provides test points with pull-up options to enable I2C communication with the FPGA. By
default, the pull-ups are not populated.
*3: GA0, GA1
This board provides pull-up or pull-down options for these connections, by default they are floating.
*4: TDI, TDO
The JTAG TDO pin is connected with a loopback to TDI through a 0 ohm resistor that is not populated by
default.
*5: PG_C2M, PG_M2C, PRSNT_M2C_N
Referring to the figure above, they all have a resistor option for either pull-up or pull-down. However, the
resistors are not populated by default, these pins are floating.
*6: Power Rails
This card provides a 12V output through the 12V0 pins and 3.3V output through the 3V3 and 3V3_AUX
pins. It is important to note that all the FMC connectors present on this board are equipped with a fuse on
the 12V0 rail. Lastly, the VADJ pins provide a 1.8V/2.5V/3.3V rail to FPGA mezzanine cards.
*7: VREF_A_M2C, VREF_B_M2C
These terminals can be monitored by test points
TP83
and
TP84
.
*8: VIO_B_M2C
Both pins J39 and K40 for this terminal can also be monitored by test point
TP81
.
