TB-KU-xxx-ACDC8K Hardware User Manual
41
Rev. 1.03
7.4.3. FMC HPC 2 (J5)
This FMC connects GTH lanes and 6 differential pairs of LA signals to banks on the FPGA.
High Speed:
Quad 226 and 227:
8 GTH lanes
2 differential clock pairs
Low Speed:
Bank 25:
6 differential LA pairs
