Inrevium TB-KU-060/075-ACDC8K Hardware User Manual Download Page 22

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TB-KU-xxx-ACDC8K Hardware User Manual

Rev. 1.03

7.2. FPGA Banks Assignments

This board supports Xilinx Kintex Ultrascale XCKU060 and XCKU085 FPGA in the FFVA1517

(FLVA1517) packages. The figure below presents bank assignments on this board.

FMC1

(8Lane)

FMC2

(8Lane)

FMC4

(8Lane)

FMC5

(8Lane)

SFP+

(4Lane)

FMC3

(8Lane)

FMC6

(4Lane)

FMC3

(8Lane)

FMC6

(4Lane)

FMC1

(8Lane)

FMC2

(8Lane)

FMC4

(4Lane)

GTH Total 32CH

GTH Total 48CH

Figure 7-6 FPGA Banks Assignments

Summary of Contents for TB-KU-060/075-ACDC8K

Page 1: ...TB KU xxx ACDC8K Hardware User Manual 1 Rev 1 03 TB KU xxx ACDC8K Hardware User Manual Rev 1 03...

Page 2: ...Release DM Rev 1 01 2015 01 19 Updated content with board pictures and FMC pinout tables DM Rev 1 02 2015 02 18 Updated Figure 4 1 7 2 7 6 7 16 KM Rev 1 03 2015 07 21 Released for 060 Added Standoffs...

Page 3: ...S TX_FAULT Selection 21 7 2 FPGA Banks Assignments 22 7 3 Clock System 23 7 3 1 VCCINT Clock Architecture 23 7 3 2 GTH Clocks 24 7 3 3 User Assigned Clocks 25 7 4 FMC Connector Interface 26 7 4 1 FMC...

Page 4: ...on 21 Figure 7 6 FPGA Banks Assignments 22 Figure 7 7 VCCINT Clock Synchronization 23 Figure 7 8 GTH and MMCX Clocks Architecture 24 Figure 7 9 User Assigned Clocks Architecture 25 Figure 7 10 High Pi...

Page 5: ...Table 7 10 FMC 5 J14 to FPGA Pinout 63 Table 7 11 FMC 6 J19 to FPGA Pinout 70 Table 7 12 SFP I2C Bus Pin Assignment 78 Table 7 13 RX_LOS TX_FAULT and RS Pin Assignment 78 Table 7 14 Micro USB Type B...

Page 6: ...ety instructions that must be followed After reading through this manual be sure to always keep it handy The following conventions are used to indicate the possibility of injury damage and classify pr...

Page 7: ...speed do not put your hand close to it Otherwise it may cause injury to persons Never touch a rotating cooling fan Do not place the product on unstable locations Otherwise it may drop or fall resulti...

Page 8: ...beyond our responsibility acts by a third party or other accidents the customer s willful or accidental misuse or use under other abnormal conditions 2 Secondary impact arising from use of this produ...

Page 9: ...le Architecture Packaging and Pinouts User Guide UG576 UltraScale Architecture GTH Transceivers User Guide UG580 UltraScale Architecture System Monitor User Guide UG583 UltraScale Architecture PCB and...

Page 10: ...ASP 134486 01 CC HPC 10 1 On Board Clocks IDT s ICS849N202I clock generator IDT ICS849N202I PLL 25MHz CMOS oscillator 40MHz crystal IDT 148 50MHz LVDS oscillator IDT 156 25MHz LVDS oscillator IDT 200...

Page 11: ...B 1 8V Fix 12pin bank 45 FMC3 GTH 8ch Quad126 127 LA Group A 36pair 1 8V Fix 72pin bank 24 46 25 47 PMOD 8pin Front panel LED 2pin Config DONE Green 1ch Red 1ch FMC1 GTH 8ch Quad224 225 LA Group A 36...

Page 12: ...rs HA 5pairs Supported 1 8 2 5 3 3V No GTH FMC Connector 6 HPC LA Group B 6pairs GTH 4Lanes FPGA DDR4 SDRAM 2 banks SFP Modules 4ch 060 not connected Power Switch Micro USB Type AB UART Power Input Co...

Page 13: ...s Board Thickness 2 0828 mm 10 Material Megtron 4 FPGA Xilinx Kintex UltraScale XCKU060 XCKU085 FFVA1517 FLVA1517 package FMC HPC CC Connector Samtec ASP 134486 01 Micro USB Connector Hirose Electric...

Page 14: ...TB KU xxx ACDC8K Hardware User Manual 14 Rev 1 03 Figure 6 1 Board Dimensions inclusive of wastable substrate top view...

Page 15: ...TB KU xxx ACDC8K Hardware User Manual 15 Rev 1 03 Figure 6 2 Board Dimensions inclusive of wastable substrate bottom view...

Page 16: ...12V x7 Total 1A x 7 7A TPS53355 In 1 5 15V Out 0 6 5 5V 30A TPS53355 In 1 5 15V Out 0 6 5 5V 30A from Sequencer from Sequencer from Sequencer UCD9090 Sequencer TLV70433 3 3V LDO 10 to power devices T...

Page 17: ...FMC_EN 3V3_EN 2V5_DDR4_EN 1V2_DDR4_EN GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 MON1 MON2 MON3 MON4 MON5 MON6 MON7 MON8 MON9 MON10 12V0 0V95_SENS 1V8_VCCAUX_SENS 1V0_MGTAVCC_SENS 1V...

Page 18: ...1 03 7 1 3 DC 4 pin Header and Binding Posts Important There are two 2 power inputs available on this board Connect one OR the other 12VDC inputs NEVER connect both power inputs simultaneously Figure...

Page 19: ...43 Power Sequencer and Monitor 1V8_FMC TP19 FPGA HP I O Banks FMC VADJ 1V2_DDR4 TP31 DDR4 and corresponding FPGA Banks 2V5_DDR4 TP30 VPP generation 0V6_VTT_DDR4 TP32 DDR4 SDRAM 1 Termination 0V6_VREF_...

Page 20: ...d for D1 Bicolor Green or Red FPGA Programming DONE signal Red Programming in progress Green Programming complete D3 Green Clock generation LOCK_IND indicator for U20 D4 Red Clock generation CLK0 BAD...

Page 21: ...ector and SFP modules are connected to the FPGA s HR 64 and 65 banks as shown in blue on this board s block diagram Figure 4 1 The SPI flash components are connected to HR bank 0 and bank 65 Banks 0 6...

Page 22: ...scale XCKU060 and XCKU085 FPGA in the FFVA1517 FLVA1517 packages The figure below presents bank assignments on this board FMC1 8Lane FMC2 8Lane FMC4 8Lane FMC5 8Lane SFP 4Lane FMC3 8Lane FMC6 4Lane FM...

Page 23: ...he FPGA The LTC6909 chip provides phase synchronized outputs with 60 offsets LTC6909 not used LMZ31710 U24 RT CLK SYNC_OUT LMZ31710 U25 RT CLK SYNC_OUT LMZ31710 U26 RT CLK SYNC_OUT LMZ31710 U27 RT CLK...

Page 24: ...P SW SW2 DIP SW OFF CLK_GLOBAL_SEL 0 FeedBack input Clock 25MHz OSC CLK_GLOBAL_CONFIG 0 Output Clock 156 25MHz CLK_GLOBAL_OE 0 No CLK_PLL_P N to Fanout Buffer CLK_PLL_BYPASS 0 PLL Mode default DIP SW...

Page 25: ...DBC DBC QBC QBC QBC DBC DBC DBC DBC QBC QBC QBC DBC DBC DBC DBC QBC QBC QBC DBC DBC DBC DBC QBC QBC QBC DBC DBC DBC DBC FMC3 FMC1 FMC_0_LA28_CC FMC_0_LA17_CC FMC_3_LA28 GC FMC_0_LA00_CC FMC_0_LA01_CC...

Page 26: ...s the standard pin assignment on FMC HPC connectors Not all the pins are connected on the FMC connectors Please follow this section for more details on all the FMC pinouts Figure 7 10 High Pin Count F...

Page 27: ...7_M2C_P GND 13 DP7_M2C_N DP4_M2C_P 14 GND DP4_M2C_N 15 GND GND 16 DP6_M2C_P GND 17 DP6_M2C_N DP5_M2C_P 18 GND DP5_M2C_N 19 GND GND 20 1 GBTCLK1_M2C_P GND 21 1 GBTCLK1_M2C_N DP1_C2M_P 22 GND DP1_C2M_N...

Page 28: ...J16 LA10_P 14 LA09_P AK13 65 64 AK16 LA10_N 15 LA09_N AK12 65 GND 16 GND GND 17 LA13_P AK18 64 64 AP19 LA14_P 18 LA13_N AK17 64 64 AP18 LA14_N 19 GND GND 20 LA17_P_CC AM19 64 GND 21 LA17_N_CC AN19 64...

Page 29: ...P 9 GND HA09_N 10 HA08_P GND 11 HA08_N HA13_P 12 GND HA13_N 13 HA12_P GND 14 HA12_N HA16_P 15 GND HA16_N 16 HA15_P GND 17 HA15_N HA20_P 18 GND HA20_N 19 HA19_P GND 20 HA19_N HB03_P 21 GND HB03_N 22 HB...

Page 30: ...65 AH14 LA12_P 15 GND 65 AJ14 LA12_N 16 LA11_P AP14 65 GND 17 LA11_N AP13 65 64 AH19 LA16_P 18 GND 64 AH18 LA16_N 19 LA15_P AJ15 65 GND 20 LA15_N AK15 65 64 AU17 LA20_P 21 GND 64 AU16 LA20_N 22 LA19_P...

Page 31: ...11 HA06_N HA11_P 12 GND HA11_N 13 HA10_P GND 14 HA10_N HA14_P 15 GND HA14_N 16 HA17_P_CC GND 17 HA17_N_CC HA18_P 18 GND HA18_N 19 HA21_P GND 20 HA21_N HA22_P 21 GND HA22_N 22 HA23_P GND 23 HA23_N HB01...

Page 32: ...er Manual 32 Rev 1 03 Figure 7 11 FMC 0 to 6 SCL SDA GA0 GA1 TDI TDO Note The above structure is identical for all FMC connectors on this board with the exception of test points and reference designat...

Page 33: ...not populated by default 5 PG_C2M PG_M2C PRSNT_M2C_N Referring to the figure above they all have a resistor option for either pull up or pull down However the resistors are not populated by default t...

Page 34: ...C 1 J2 This FMC connects GTH lanes and all of the available LA signals to banks on the FPGA High Speed Quad 224 and 225 8 GTH lanes 2 differential clock pairs Low Speed Bank 44 16 differential LA pair...

Page 35: ...3 DP4_M2C_N 15 GND GND 16 DP6_M2C_P AV2 224 GND 17 DP6_M2C_N AV1 224 224 AW4 DP5_M2C_P 18 GND 224 AW3 DP5_M2C_N 19 GND GND 20 1 GBTCLK1_M2C_P AP10 224 GND 21 1 GBTCLK1_M2C_N AP9 224 225 AN8 DP1_C2M_P...

Page 36: ...N AU22 44 GND 13 GND 45 AW25 LA10_P 14 LA09_P AV23 44 45 AW26 LA10_N 15 LA09_N AW23 44 GND 16 GND GND 17 LA13_P AH24 45 45 AJ25 LA14_P 18 LA13_N AJ24 45 45 AK25 LA14_N 19 GND GND 20 LA17_P_CC AM27 45...

Page 37: ...HA08_N HA13_P 12 GND HA13_N 13 HA12_P GND 14 HA12_N HA16_P 15 GND HA16_N 16 HA15_P GND 17 HA15_N HA20_P 18 GND HA20_N 19 HA19_P GND 20 HA19_N HB03_P 21 GND HB03_N 22 HB02_P GND 23 HB02_N HB05_P 24 GND...

Page 38: ...44 AV24 LA12_P 15 GND 44 AW24 LA12_N 16 LA11_P AT23 44 GND 17 LA11_N AT24 44 45 AV26 LA16_P 18 GND 45 AV27 LA16_N 19 LA15_P AL20 44 GND 20 LA15_N AM20 44 45 AH26 LA20_P 21 GND 45 AJ26 LA20_N 22 LA19_P...

Page 39: ...12 GND HA11_N 13 HA10_P GND 14 HA10_N HA14_P 15 GND HA14_N 16 HA17_P_CC GND 17 HA17_N_CC HA18_P 18 GND HA18_N 19 HA21_P GND 20 HA21_N HA22_P 21 GND HA22_N 22 HA23_P GND 23 HA23_N HB01_P 24 GND HB01_N...

Page 40: ...TAG TDO pin is connected with a loopback to TDI through a 0 ohm resistor that is not populated by default 5 PG_C2M PG_M2C PRSNT_M2C_N These all have a pull up or pull down resistor option However the...

Page 41: ...nual 41 Rev 1 03 7 4 3 FMC HPC 2 J5 This FMC connects GTH lanes and 6 differential pairs of LA signals to banks on the FPGA High Speed Quad 226 and 227 8 GTH lanes 2 differential clock pairs Low Speed...

Page 42: ...3 DP4_M2C_N 15 GND GND 16 DP6_M2C_P AK2 226 GND 17 DP6_M2C_N AK1 226 226 AL4 DP5_M2C_P 18 GND 226 AL3 DP5_M2C_N 19 GND GND 20 1 GBTCLK1_M2C_P AF10 226 GND 21 1 GBTCLK1_M2C_N AF9 226 227 AE4 DP1_C2M_P...

Page 43: ...9 LA01_N_CC LA06_P 10 GND LA06_N 11 LA05_P GND 12 LA05_N GND 13 GND LA10_P 14 LA09_P LA10_N 15 LA09_N GND 16 GND GND 17 LA13_P LA14_P 18 LA13_N LA14_N 19 GND GND 20 LA17_P_CC GND 21 LA17_N_CC LA18_P_...

Page 44: ...HA08_N HA13_P 12 GND HA13_N 13 HA12_P GND 14 HA12_N HA16_P 15 GND HA16_N 16 HA15_P GND 17 HA15_N HA20_P 18 GND HA20_N 19 HA19_P GND 20 HA19_N HB03_P 21 GND HB03_N 22 HB02_P GND 23 HB02_N HB05_P 24 GND...

Page 45: ..._N 25 AT34 LA08_P 12 GND 25 AU34 LA08_N 13 LA07_P GND 14 LA07_N 25 AV33 LA12_P 15 GND 25 AV34 LA12_N 16 LA11_P GND 17 LA11_N 25 AT35 LA16_P 18 GND 25 AU35 LA16_N 19 LA15_P GND 20 LA15_N LA20_P 21 GND...

Page 46: ...12 GND HA11_N 13 HA10_P GND 14 HA10_N HA14_P 15 GND HA14_N 16 HA17_P_CC GND 17 HA17_N_CC HA18_P 18 GND HA18_N 19 HA21_P GND 20 HA21_N HA22_P 21 GND HA22_N 22 HA23_P GND 23 HA23_N HB01_P 24 GND HB01_N...

Page 47: ...TAG TDO pin is connected with a loopback to TDI through a 0 ohm resistor that is not populated by default 5 PG_C2M PG_M2C PRSNT_M2C_N These all have a pull up or pull down resistor option However the...

Page 48: ...C 3 J8 This FMC connects GTH lanes and all of the available LA signals to banks on the FPGA High Speed Quad 126 and 127 8 GTH lanes 2 differential clock pairs Low Speed Bank 24 16 differential LA pair...

Page 49: ...DP4_M2C_N 15 GND GND 16 DP6_M2C_P W38 127 GND 17 DP6_M2C_N W39 127 127 V36 DP5_M2C_P 18 GND 127 V37 DP5_M2C_N 19 GND GND 20 1 GBTCLK1_M2C_P AB32 126 GND 21 1 GBTCLK1_M2C_N AB33 126 126 AG34 DP1_C2M_P...

Page 50: ...5_N AL32 24 GND 13 GND 25 AM36 LA10_P 14 LA09_P AU32 24 25 AM37 LA10_N 15 LA09_N AV32 24 GND 16 GND GND 17 LA13_P AU37 25 25 AR37 LA14_P 18 LA13_N AV37 25 25 AT37 LA14_N 19 GND GND 20 LA17_P_CC AP36 2...

Page 51: ...HA08_N HA13_P 12 GND HA13_N 13 HA12_P GND 14 HA12_N HA16_P 15 GND HA16_N 16 HA15_P GND 17 HA15_N HA20_P 18 GND HA20_N 19 HA19_P GND 20 HA19_N HB03_P 21 GND HB03_N 22 HB02_P GND 23 HB02_N HB05_P 24 GND...

Page 52: ...24 AP30 LA12_P 15 GND 24 AP31 LA12_N 16 LA11_P AR31 24 GND 17 LA11_N AR32 24 25 AU36 LA16_P 18 GND 25 AV36 LA16_N 19 LA15_P AN33 24 GND 20 LA15_N AP33 24 25 AV38 LA20_P 21 GND 25 AV39 LA20_N 22 LA19_P...

Page 53: ...12 GND HA11_N 13 HA10_P GND 14 HA10_N HA14_P 15 GND HA14_N 16 HA17_P_CC GND 17 HA17_N_CC HA18_P 18 GND HA18_N 19 HA21_P GND 20 HA21_N HA22_P 21 GND HA22_N 22 HA23_P GND 23 HA23_N HB01_P 24 GND HB01_N...

Page 54: ...TAG TDO pin is connected with a loopback to TDI through a 0 ohm resistor that is not populated by default 5 PG_C2M PG_M2C PRSNT_M2C_N These all have a pull up or pull down resistor option However the...

Page 55: ...HPC 4 J11 This FMC connects GTH lanes and 6 differential pairs of LA signals to banks on the FPGA High Speed Quad 228 XCKU060 Quad 228 and 229 XCKU085 4 GTH lanes XCKU060 8 GTH lanes XCKU085 2 differe...

Page 56: ...8 W3 DP4_M2C_N 15 GND GND 16 DP6_M2C_P Y2 228 GND 17 DP6_M2C_N Y1 228 228 AB2 DP5_M2C_P 18 GND 228 AB1 DP5_M2C_N 19 GND GND 20 1 GBTCLK1_M2C_P W8 228 GND 21 1 GBTCLK1_M2C_N W7 228 229 085 P6 DP1_C2M_P...

Page 57: ...CC GND 9 LA01_N_CC LA06_P 10 GND LA06_N 11 LA05_P GND 12 LA05_N GND 13 GND LA10_P 14 LA09_P LA10_N 15 LA09_N GND 16 GND GND 17 LA13_P LA14_P 18 LA13_N LA14_N 19 GND GND 20 LA17_P_CC GND 21 LA17_N_CC L...

Page 58: ...HA08_N HA13_P 12 GND HA13_N 13 HA12_P GND 14 HA12_N HA16_P 15 GND HA16_N 16 HA15_P GND 17 HA15_N HA20_P 18 GND HA20_N 19 HA19_P GND 20 HA19_N HB03_P 21 GND HB03_N 22 HB02_P GND 23 HB02_N HB05_P 24 GND...

Page 59: ..._N 44 AD20 LA08_P 12 GND 44 AD21 LA08_N 13 LA07_P GND 14 LA07_N 44 AE20 LA12_P 15 GND 44 AE21 LA12_N 16 LA11_P GND 17 LA11_N 44 AE22 LA16_P 18 GND 44 AF22 LA16_N 19 LA15_P GND 20 LA15_N LA20_P 21 GND...

Page 60: ...12 GND HA11_N 13 HA10_P GND 14 HA10_N HA14_P 15 GND HA14_N 16 HA17_P_CC GND 17 HA17_N_CC HA18_P 18 GND HA18_N 19 HA21_P GND 20 HA21_N HA22_P 21 GND HA22_N 22 HA23_P GND 23 HA23_N HB01_P 24 GND HB01_N...

Page 61: ...TDI TDO The JTAG TDO pin is connected with a loopback to TDI through a 0 ohm resistor that is not populated by default 5 PG_C2M PG_M2C PRSNT_M2C_N These all have a pull up or pull down resistor option...

Page 62: ...FMC HPC 5 J14 This FMC connects GTH lanes XCKU085 only and 6 differential pairs of LA signals to banks on the FPGA High Speed No GTH XCKU060 Quad 230 and 231 XCKU085 8 GTH lanes XCKU085 2 differentia...

Page 63: ...GND GND 16 DP6_M2C_P L4 230 085 GND 17 DP6_M2C_N L3 230 085 230 085 M2 DP5_M2C_P 18 GND 230 085 M1 DP5_M2C_N 19 GND GND 20 1 GBTCLK1_M2C_P M10 230 085 GND 21 1 GBTCLK1_M2C_N M9 230 085 231 085 F6 DP1...

Page 64: ..._P_CC GND 9 LA01_N_CC LA06_P 10 GND LA06_N 11 LA05_P GND 12 LA05_N GND 13 GND LA10_P 14 LA09_P LA10_N 15 LA09_N GND 16 GND GND 17 LA13_P LA14_P 18 LA13_N LA14_N 19 GND GND 20 LA17_P_CC GND 21 LA17_N_C...

Page 65: ...HA08_N HA13_P 12 GND HA13_N 13 HA12_P GND 14 HA12_N HA16_P 15 GND HA16_N 16 HA15_P GND 17 HA15_N HA20_P 18 GND HA20_N 19 HA19_P GND 20 HA19_N HB03_P 21 GND HB03_N 22 HB02_P GND 23 HB02_N HB05_P 24 GND...

Page 66: ..._N 45 AE27 LA08_P 12 GND 45 AF27 LA08_N 13 LA07_P GND 14 LA07_N 45 AD26 LA12_P 15 GND 45 AE26 LA12_N 16 LA11_P GND 17 LA11_N 45 AF25 LA16_P 18 GND 45 AG25 LA16_N 19 LA15_P GND 20 LA15_N LA20_P 21 GND...

Page 67: ...12 GND HA11_N 13 HA10_P GND 14 HA10_N HA14_P 15 GND HA14_N 16 HA17_P_CC GND 17 HA17_N_CC HA18_P 18 GND HA18_N 19 HA21_P GND 20 HA21_N HA22_P 21 GND HA22_N 22 HA23_P GND 23 HA23_N HB01_P 24 GND HB01_N...

Page 68: ...TDI TDO The JTAG TDO pin is connected with a loopback to TDI through a 0 ohm resistor that is not populated by default 5 PG_C2M PG_M2C PRSNT_M2C_N These all have a pull up or pull down resistor optio...

Page 69: ...r Manual 69 Rev 1 03 7 4 7 FMC HPC 6 J19 This FMC connects GTH lanes and 6 differential pairs of LA signals to banks on the FPGA High Speed Quad 128 4 GTH lanes 2 differential clock pairs Low Speed Ba...

Page 70: ...GND 13 DP7_M2C_N DP4_M2C_P 14 GND DP4_M2C_N 15 GND GND 16 DP6_M2C_P GND 17 DP6_M2C_N DP5_M2C_P 18 GND DP5_M2C_N 19 GND GND 20 1 GBTCLK1_M2C_P P32 128 GND 21 1 GBTCLK1_M2C_N P33 128 128 U34 DP1_C2M_P...

Page 71: ...9 LA01_N_CC LA06_P 10 GND LA06_N 11 LA05_P GND 12 LA05_N GND 13 GND LA10_P 14 LA09_P LA10_N 15 LA09_N GND 16 GND GND 17 LA13_P LA14_P 18 LA13_N LA14_N 19 GND GND 20 LA17_P_CC GND 21 LA17_N_CC LA18_P_...

Page 72: ...HA08_N HA13_P 12 GND HA13_N 13 HA12_P GND 14 HA12_N HA16_P 15 GND HA16_N 16 HA15_P GND 17 HA15_N HA20_P 18 GND HA20_N 19 HA19_P GND 20 HA19_N HB03_P 21 GND HB03_N 22 HB02_P GND 23 HB02_N HB05_P 24 GND...

Page 73: ..._N 24 AH28 LA08_P 12 GND 24 AJ28 LA08_N 13 LA07_P GND 14 LA07_N 24 AE30 LA12_P 15 GND 24 AF30 LA12_N 16 LA11_P GND 17 LA11_N 24 AF29 LA16_P 18 GND 24 AG29 LA16_N 19 LA15_P GND 20 LA15_N LA20_P 21 GND...

Page 74: ...12 GND HA11_N 13 HA10_P GND 14 HA10_N HA14_P 15 GND HA14_N 16 HA17_P_CC GND 17 HA17_N_CC HA18_P 18 GND HA18_N 19 HA21_P GND 20 HA21_N HA22_P 21 GND HA22_N 22 HA23_P GND 23 HA23_N HB01_P 24 GND HB01_N...

Page 75: ...O The JTAG TDO pin is connected with a loopback to TDI through a 0 ohm resistor that is not populated by default 5 PG_C2M PG_M2C PRSNT_M2C_N These all have a pull up or pull down resistor option Howev...

Page 76: ...SU DQSL DQSL DMU DML DDR4 SDRAM 4Gbit U7 DDR4 SDRAM 4Gbit U8 HP Bank68 HP Bank67 HP Bank66 FPGA DQU 7 0 DQL 7 0 DQSU DQSU DQSL DQSL DMU DML DQU 7 0 DQL 7 0 DQSU DQSU DQSL DQSL DMU DML DQU 7 0 DQL 7 0...

Page 77: ...n the FPGA They also connect to an I2C bus through TI s PCA9544A 4 to 1 I2C MUX with four available interrupt inputs for each of the downstream pairs Available on the same component is a global interr...

Page 78: ...connectors which can be depopulated as required Table 7 13 RX_LOS TX_FAULT and RS Pin Assignment SFP Connector Signal Name Description FPGA Bank Pin 1 J21 SFP_1_RX_L TX_FA_FPGA_OD Selected RX_LOS or...

Page 79: ...ignals are connected to the FPGA s single ended pins on Bank 24 Provided below is a table indicating where the signals connect Both the UART transmit and receive data signals are connected as well as...

Page 80: ...d to the VBATT pin which serves as a battery backup supply for the FPGA s internal volatile memory that stores the key for AES decryption More information is available in Xilinx s UltraScale configura...

Page 81: ...transfer rate mode Bank0 Bank65 D00 D01 D02 D03 D04 D05 D06 D07 QSPI N25Q256 QSPI N25Q256 CFGBVS VCCO HR VCCO_0 VCCO_65 Voltage Detect 2 08V VCCO HR VCCO HR CCLK VCCO HR 1 8V 2 5V 3 3V Selectable VCCO...

Page 82: ...AF13 CLK_FPGA_CCLK 0 AC11 Xilinx Core User IO SPIFLASH_ZYNQ_CS_N 47 P29 SPIFLASH_ZYNQ_IO_0 47 N29 SPIFLASH_ZYNQ_IO_1 47 L32 SPIFLASH_ZYNQ_IO_2 47 L33 SPIFLASH_ZYNQ_IO_3 47 R30 SPIFLASH_ZYNQ_CFG_OD 65...

Page 83: ...round signals and eight I O XCKU075 Bank 44 and 45 PMOD_ 7 0 _FPGA TI TXS0108E Voltage Translator 1 8V 3 3V PMOD_ 7 0 Pmod 2x6 Male 0 1 Straight Header SMT Molex 15912120 J31 Figure 7 17 Pmod Connecti...

Page 84: ...tted LEDs Pin Assignment LED RefDes Color Signal Name FPGA Bank FPGA Pin D12 Green GRN_LED_1 66 A12 D13 Green GRN_LED_5 66 H13 D14 Red RED_LED_1 67 H16 D15 Red RED_LED_5 67 K17 D16 Green GRN_LED_2 66...

Page 85: ...16 SWITCH_8 67 P19 SW19 SWITCH_9 67 P18 SWITCH_10 68 A23 SWITCH_11 68 C24 SWITCH_12 68 F22 SW20 SWITCH_13 68 H22 SWITCH_14 68 L22 SWITCH_15 68 J21 SWITCH_16 68 R23 7 12 2 Push Switches The board also...

Page 86: ...tches Structure The signals output logic high by default when there is no jumper connected Connect an odd numbered pin to the even numbered pin across from it to output a logic low to the FPGA The hea...

Page 87: ...1 1 2 POR Override ON OFF 2 SW2 ALL OFF Video Clock setting 3 SW17 18 19 20 ALL OFF User DIP Switches setting 4 J44 Open FMC_HR_Bank voltage 1 8V 2 5V 3 3V 5 J40 Open PMBUS_ADDR0 GND_90 9K 1 GND_41 2K...

Page 88: ...TB KU xxx ACDC8K Hardware User Manual 88 Rev 1 03 8 2 Power Sequencer Timings Figure 8 2 Power Sequencer Default Settings...

Page 89: ...Inrevium Company URL http solutions inrevium com http solutions inrevium com jp E mail psd support teldevice co jp HEAD Quarter Yokohama East Square 1 4 Kinko cho Kanagawa ku Yokohama City Kanagawa Ja...

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