TB-KU-xxx-ACDC8K Hardware User Manual
3
Rev. 1.03
Table of Contents
1.
Related Documents and Accessories ......................................................................................... 9
2.
Overview ...................................................................................................................................... 9
3.
Feature ...................................................................................................................................... 10
4.
Block Diagram ............................................................................................................................ 11
5.
External View of the Board ........................................................................................................ 12
6.
Board Specifications .................................................................................................................. 13
7.
Description of Components ....................................................................................................... 16
7.1.
Power Supply Structure ............................................................................................................ 16
7.1.1.
Power Sequencing ............................................................................................................ 17
7.1.2.
Power Input connectors .................................................................................................... 17
7.1.3.
DC 4-pin Header and Binding Posts ................................................................................. 18
7.1.4.
Voltage Rails Test Points .................................................................................................. 19
7.1.5.
Power and Miscellaneous LEDs ....................................................................................... 20
7.1.6.
Board Power Button .......................................................................................................... 21
7.1.7.
FPGA HR Bank Voltage Selection .................................................................................... 21
7.1.8.
HR Banks Voltage and SFP+ RX_LOS/TX_FAULT Selection .......................................... 21
7.2.
FPGA Banks Assignments ....................................................................................................... 22
7.3.
Clock System ........................................................................................................................... 23
7.3.1.
VCCINT Clock Architecture .............................................................................................. 23
7.3.2.
GTH Clocks ...................................................................................................................... 24
7.3.3.
User Assigned Clocks ....................................................................................................... 25
7.4.
FMC Connector Interface ......................................................................................................... 26
7.4.1.
FMC HPC 0 (J1) ............................................................................................................... 26
7.4.2.
FMC HPC 1 (J2) ............................................................................................................... 34
7.4.3.
FMC HPC 2 (J5) ............................................................................................................... 41
7.4.4.
FMC HPC 3 (J8) ............................................................................................................... 48
7.4.5.
FMC HPC 4 (J11) ............................................................................................................. 55
7.4.6.
FMC HPC 5 (J14) ............................................................................................................. 62
7.4.7.
FMC HPC 6 (J19) ............................................................................................................. 69
7.5.
DDR4 SDRAM .......................................................................................................................... 76
7.6.
SFP+ Connectors ..................................................................................................................... 77
7.7.
USB to UART Controller ........................................................................................................... 79
7.8.
Battery ...................................................................................................................................... 80
7.9.
Dual Quad (x8) SPI Flash ........................................................................................................ 81
7.10.
JTAG and Pmod Interface .................................................................................................... 82
7.10.1.
JTAG Connector ............................................................................................................... 82
7.10.2.
Pmod Interface ................................................................................................................. 83
7.11.
General Purpose LEDs......................................................................................................... 84
7.12.
General Purpose Switches ................................................................................................... 85
7.12.1.
DIP Switches..................................................................................................................... 85
7.12.2.
Push Switches .................................................................................................................. 85
7.12.3.
Jumper Switches .............................................................................................................. 86
8.
Appendix .................................................................................................................................... 87
8.1.
Default Settings ........................................................................................................................ 87
8.2.
Power Sequencer Timings ....................................................................................................... 88
