User’s Manual
6-31
05.99
On-Chip Peripheral Components
C513AO
6.3.1 Multiprocessor Communications
Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data
bits are received. The 9th one goes into RB8. Then comes a stop bit. The port can be programmed
such that when the stop bit is received, the serial port interrupt will be activated only if RB8 = 1. This
feature is enabled by setting bit SM2 in SCON. One use of this feature in multiprocessor systems
is described here.
When the master processor wants to transmit a block of data to one of several slaves, it first sends
out an address byte which identifies the target slave. An address byte differs from a data byte in
that the 9th bit is “1” in an address byte and “0” in a data byte. With SM2 = 1, no slave will be
interrupted by a data byte. An address byte, however, will interrupt all slaves, so that each slave
can examine the received byte to determine if it is being addressed. The addressed slave will clear
its SM2 bit and prepare to receive data bytes. The slaves which weren't being addressed keep their
SM2s set and ignore the incoming data bytes.
SM2 has no effect in Mode 0; in Mode 1, it can be used to check the validity of the stop bit. In a
Mode 1 reception, if SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is
received.
6.3.2 Serial Port Registers
The serial port control and status register is the special function register SCON. This register
contains not only the mode selection bits, but also the 9th data bit for transmit and receive (TB8 and
RB8), and the serial port interrupt bits (TI and RI).
SBUF is the receive and transmit buffer of the serial interface. Writing to SBUF loads the transmit
register and initiates transmission. Reading out SBUF accesses a physically separate receive
register.
