Reset / System Clock
C513AO
User’s Manual
5-3
05.99
5.2
Fast Internal Reset after Power-On
The C513AO uses the Oscillator Watchdog unit for a fast internal reset procedure after power-on.
Figure 5-2 shows the power-on sequence under control of the Oscillator Watchdog.
Normally, devices in the 8051 microcontroller family do not enter their default reset state before the
on-chip oscillator starts. The reason is that the external reset signal must be internally synchronized
and processed to bring the device into the correct reset state. Especially if a crystal is used, the start
up time of the oscillator is relatively long (typ. 10 ms). During this time period, the pins have an
undefined state which could have severe effects, especially to actuators connected to port pins.
In the C513AO, the Oscillator Watchdog unit avoids this problem. With this device, after power-on,
the Oscillator Watchdog’s RC oscillator starts working within a very short start-up time (typ. less
than 2 ms). Following this, the watchdog circuitry detects a failure condition for the on-chip oscillator
because this has not yet started (a failure is always recognized if the watchdog’s RC oscillator runs
faster than the on-chip oscillator). As long as this condition is detected, the watchdog uses the RC
oscillator output as clock source for the chip rather than the on-chip oscillator's output. This allows
correct resetting of the part and brings all ports to the defined state (see Figure 5-2).
Under worst case conditions (fast
V
DD
rise time, such as 1
µ
s, measured from
V
DD
= 4.25 V up to
stable port condition), the delay between power-on and the correct port reset state is:
– Typical: 18
µ
s
– Maximum: 34
µ
s
The RC oscillator will already run at a
V
DD
below 4.25V (lower specification limit). Therefore, at
slower
V
DD
rise times, the delay time will be less than the two values given above.
After the on-chip oscillator has finally started, the Oscillator Watchdog detects the correct function;
then the watchdog still holds the reset active for a time period of max. 768 cycles of the RC oscillator
clock to allow the oscillation of the on-chip oscillator to stabilize (Figure 5-2, II). Subsequently, the
clock is supplied by the on-chip oscillator and the oscillator watchdog's reset request is released
(Figure 5-2, III). However, an externally applied reset still remains active (Figure 5-2, IV) and the
device does not start program execution (Figure 5-2, V) before the external reset is also released.
Although the Oscillator Watchdog provides a fast internal reset, it is additionally necessary to apply
the external reset signal when powering up for the following reasons:
– Termination of software Power-Down Mode
– Reset of the status flag OWDS which is set by the Oscillator Watchdog during the power up
sequence.
Using a crystal or ceramic resonator for clock generation, the external reset signal must be held
active at least until the on-chip oscillator has started and the internal watchdog reset phase is
completed (after Phase III in Figure 5-2). When an external clock generator is used, Phase II is very
short. Therefore, an external reset time of typically 1 ms is sufficient in most applications.
For reset time generation at power-on, an external capacitor can be applied to the RESET pin.
