User’s Manual
9-3
05.99
Power Saving Modes
C513AO
9.1
Idle Mode
In Idle Mode, the oscillator of the C513AO continues to run; but, the CPU is gated off from the clock
signal. However, the interrupt system, the serial port, the Synchronous Serial Channel (SSC)
interface, and all timers are still provided with the clock. CPU status is preserved in its entirety: the
stack pointer, program counter, program status word, accumulator, and all other registers maintain
their data during Idle Mode.
The reduction of power consumption which can be achieved by this feature depends on the number
of peripherals running.
If all timers are stopped and the SSC and serial interfaces are not running, maximum power
reduction can be achieved. This state is also the test condition for Idle Mode
I
DD
.
The user must take care which peripheral should continue to run and which are to be stopped during
Idle Mode. The state of all port pins – both the pins controlled by their latches and those controlled
by their secondary functions – also depends on the status of the controller when entering Idle Mode.
Normally, the port pins hold the logical state they had at the time Idle Mode was activated. If some
pins are programmed to serve their alternative functions, they still continue to output during Idle
Mode if the assigned function is on. This applies to the serial interface in case it cannot finish
reception or transmission during normal operation. The control signals ALE and PSEN are held at
logic high levels.
Table 9-1
Status of External Pins During Idle Mode and Power-down Mode
Outputs
Last Instruction Executed from
Internal Code Memory
Last Instruction Executed from
External Code Memory
Idle
Power-down
Idle
Power-down
ALE
High
Low
High
Low
PSEN
High
Low
High
Low
PORT 0
Data
Data
Float
Float
PORT 1
Data/alternative
outputs
Data/last output
Data/alternative
outputs
Data/last output
PORT 2
Data
Data
Address
Data
PORT 3
Data/alternative
outputs
Data/last output
Data/alternative
outputs
Data/last output
