User’s Manual
7-4
05.99
Interrupt System
C513AO
7.2
Interrupt Registers
7.2.1 Interrupt Enable Registers
Each interrupt vector can be enabled or disabled individually by setting or clearing the
corresponding bit in the SFR IE (Interrupt Enable). This register also contains the global disable bit
EA, which can be cleared/set to disable/enable all interrupts.
Special Function Registers IE (Address A8H)
Reset Value: 00H
Bit
Function
EA
Enable/Disable All Interrupts.
If EA = 0, no interrupt will be acknowledged.
If EA = 1, each interrupt source is individually enabled or disabled by setting or
clearing its enable bit.
ESSC
SSC Interrupt Enable.
If ESSC = 0, the interrupt of the Synchronous Serial Channel (SSC) is disabled.
ET2
Timer 2 Interrupt Enable.
If ET2 = 0, the Timer 2 interrupt is disabled.
ES
USART Serial Channel Interrupt Enable.
If ES = 0, the serial channel interrupt is disabled.
ET1
Timer 1 Overflow Interrupt Enable.
If ET1 = 0, the Timer 1 interrupt is disabled.
EX1
External interrupt 1 Enable.
If EX1 = 0, the external interrupt 1 is disabled.
ET0
Timer 0 overflow interrupt Enable.
If ET0 = 0, the Timer 0 interrupt is disabled.
EX0
External interrupt 0 Enable.
If EX0 = 0, the external interrupt 0 is disabled.
MSB
LSB
IE
EA
ESSC
ET2
ES
ET1
EX1
ET0
EX0
7
6
5
4
3
2
1
0
Bit No.
A8H
