RMV Operations Manual Revision Copyright illunis LLC, 2014
Page 74
5.0: Image Processing
Overview
The RMV FPGA implements image processing features that are very useful to
many imaging applications. These include reordering of the sensor image data, cor-
rection of pixel defects and responses, mapping the video data using a programmable
look up table, and video analysis tools.
The flow of image data from the CCD Taps to the LVDS output drivers is as follows:
a) Image data is read from the sensor in a raw form. The image data is represented as 12 bits
per pixel. The data is processed as 12 bits until the last stages where it is formatted into the
selected Camera Link format.
b) Video Tap data is reorder to create a single corrected image
c) Video data is passed through the detectors in the reordered but unmodified format
d) The Video data is then optionally corrected for gross defects
d) The Video data is then optionally corrected for column gain.
d) The data is then passed through an optional look up table (LUT) . The LUT converts the 12-
bit video data to any 12-bit value.
g) The final processing stage formats the video data for the output LVDS circuitry. This stage
permits one or two channel output, bit and tap flipping, 8 and 12 bit/pixel formatting for cam-
era link. This stage also provides the test pattern and on screen display functions
Notes: PIO = parallel IO from microprocessor.
PIO
(a)
(b)
(c)
(d)
(e)
(f)
Tap
Reorder
From
ADC A
ADC B
Pixel
Defect
Correction
Image
Detectors
Flat Field
Correction
Look Up
Tables
Camera
Link
Format
Column
Memories
On
Screen
Display
(g)
Histogram
