35
Tsi620 Evaluation Board User Manual
60D7000_MA001_03
Intergrated Device Technology
www.idt.com
Figure 11: Location of Switches and Connections
T
si6
20 EV
B Pl
ac
em
en
t Top
View
S1
S2
S3
S4
J14
-FPGA
SFP
J
15-
DSP SFP
U35
M
in
i-U
SB
U2
6
FPGA
-R
J
45
U3
4
Gi
gE-
R
J45
SW
2
ON
/O
F
F
J4
: M
ic
tor
U2
9
+12
V
in
J2
: DS
P
Em
u
la
to
r P
o
rt
J1
0
Tsi
62
0 JTA
G
P1:
A
M
C
Sl
o
t
J5
F
P
G
A
A
cti
ve
Se
rial
Pr
ogr
amm
in
g
U2
1
U2
2
2-
Ch
ar
s
LED Dis
p
lay
SW1
:
So
ft-Re
set
SW
3
:
Sy
st
em-Re
set
J1
3: S
M
A
Ex
C
L
K 32.
72
M
H
z
DSP-GigE
AMC-GigE
J7
/J
8
&
J11
/J
12
S
M
A to
FP
GA
S5
JN2
JN1
JN3
Ts
i62
0 E
V
B P
lacem
en
t Bottom
Vie
w
Pr
PM
C
Co
nnect
or
J9
FPGA
JTAG