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Tsi620 Evaluation Board User Manual
60D7000_MA001_03
Intergrated Device Technology
www.idt.com
1.3.1.3
XGMII FPGA Interface
•
Tx/Rx clocking: synchronous 156.25, 125, or 62.5 MHz
•
Tx_CLK: source to FPGA for RIO-XGMII interface clocking
•
Signaling: HSTL-1.5V DDR
•
Transmit: Tx_CLK, Tx_D[31:0], Tx_CTL[3:0], Tx_PHY_DISABLE
•
Receive: Rx_CLK, Rx_D[31:0], Rx_CTL[3:0], Rx_ERROR
•
The FPGA provides both on-chip parallel and serial termination for the XGMII interface.
Note: This feature is not supported on revision 1 of the prototype board.
1.3.1.4
JTAG, GPIO, and I2C
•
Tsi620 supports I2C master mode or optional slave mode with jumper setting
•
External socket I2C device with 8 DIP package (AT24C64B)
•
Supports I2C configuration loading
•
Uses FT2233D, USB to UART/FIFO controller, as USB to JTAG port converter
•
Supports Tsi620 register access through JTAG port (mini-USB connector)
Table 2: PCI Interface Power-Up Configuration Setting
Pin Name
Setting
Description
PCI_RSTDIR
1
1 = PCI_RSTn is an output
PCI_M66EN
1/0
1 = 66MHz (PrPMC card could force it to 0 to 33 MHz operation using
S3 bit [1])
PCI_PLL_BYPASS
0
0 = PCI PLL is enabled
PCI_ARBEN
1
1 = PCI internal arbiter is used
PCI_HOLD_BOOT
0
0 = Release PCI software reset immediately after a Tsi620 reset is
completed
SPARE[1:0]
00
00 = Tsi620 (pull-up/down required for BOM selection)
Table 3: PrPMC Interrupt Routing
Interrupt Line
Source
Description
INTA
Tsi620
Tsi620 interrupt output to PrPMC
INTB
FPGA
FPGA real-time events
INTC
System Controller
System administration coordination
INTD
DSP
DSP real-time events