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Tsi620 Evaluation Board User Manual
60D7000_MA001_03
Intergrated Device Technology
www.idt.com
1.3.4.2
AFS600-FBGA256 Implementation
•
Bank 0: 1.8V LVCOMS1V8
•
Bank 1: 3.3V LVTTL, LVCOMS, LVPECL
•
Bank 2: 2.5V LVCOMS2V5
•
Bank 4: 3.3V LVTTL, LVCOMS, LVPECL
•
Analog Bank: 0 ~ 12V power monitoring
•
Power: 3.3V_MP only with max. 100mA
1.3.4.3
Reset Control
The Actel Flash FPGA is used on the evaluation board to implement the module management
controller of the AMC interface. The Actel FPGA also functions as the central reset controller to
handle the reset control glue logic.
Reset Control Requirement
Reset Control Logic
•
System management controller: Actel AFS256-FG256, Flash-based mixed signal FPGA
•
Supports multi-volt device control
Table 6: Major Components Reset Signal List
Devices
Reset Signal
Logic
Function
Tsi620
CHIP_RSTn
3.3VLVTTL
Tsi620 chip reset
Tsi620
BLOCK_RSTn
3.3VLVTTL
Tsi620 block reset
TI-DSP
PORz
1.8VLVCOMS
DSP power-on reset. Held low >1 ms after power and clk
TI-DSP
XWRSTz
1.8VLVCOMS
DSP warm reset. No affect on PLL and emulation
FPGA
HRSTn
3.3VLVTTL
FPGA power-on reset and trigger device reset
FPGA
SRSTn
3.3VLVTTL
FPGA soft reset and no affect to PLL
V8221
HRESETn
3.3VLVTTL
GigE PHY reset