IDT 89HPES34H16, User Manual, Page: 45 / 182

IDT Clocking, Reset, and Initialization Clock Operation
PES34H16 User Manual 3 - 5 October 30, 2008
Notes
Fundamental Reset
A fundamental reset may be initiated by any of the following conditions:
– A cold reset initiated by a power-on and the assertion of the PCI Express Reset (PERSTN) input
pin.
– A warm reset initiated by the assertion of the PCI Express Reset (PERSTN) input pin while power
is on.
– A warm reset initiated by the writing of a one to the Fundamental Reset (FRST) bit in the Switch
Control (SWCTL) register.
The following reset sequence is executed.
1. Wait for the fundamental reset condition to clear (e.g., negation of PERSTN).
2. On negation of PERSTN, sample the boot configuration signals listed in Table 3.2. If PERSTN was
not asserted, use the previously sampled boot configuration signal values (e.g., when a fundamental
reset is the result of a one being written to the FRST bit in the SWCTL register).
– Examine the state of the sampled SWMODE[3:0] signals to determine the switch operating mode.
3. The PLL and SerDes are initialized.
4. Link training begins. While link training is in progress, proceed to step 5.
5. If the Reset Halt (RSTHALT) pin is asserted, the RSTHALT bit in the SWSTS register is set.
6. If the switch operating mode is not a test mode, then the reset signal to the PCI Express stacks and
associated logic is negated but they are held in a quasi-reset state in which the following actions
occur.
– All links enter an active link training state within 20ms of the clearing of the fundamental reset
condition.
– Within 100ms of the clearing of the fundamental reset condition, all of the stacks are able to
process configuration transactions and respond to these transactions with a configuration request
retry status completion. All other transactions are ignored.
7. The master SMBus operating frequency is determined.
– The state of the MSMBSMODE signal is examined. If it is asserted, then the master SMBus is
initialized to operate at 100 KHz rather than 400 KHz.
8. The slave SMBus is taken out of reset and initialized. The slave SMBus address specified by the
SSMBADDR[5,3:1] pins is used.
9. The master SMBus is taken out of reset and initialized.
10. If the selected switch operating mode is one that requires initialization from the serial EEPROM, then
the contents of the serial EEPROM are read and the appropriate PES34H16 registers are updated.
– If an error is detected during loading of the serial EEPROM, then loading of the serial EEPROM
is aborted and the RSTHALT bit is set in the SWCTL register. Error information is recorded in the
SMBUSSTS register.
– When serial EEPROM initialization completes or when an error is detected, the EEPROMDONE
bit in the SMBUSSTS register is set.
11. If the Reset Halt (RSTHALT) bit is set in the SWCTL register, all of the logic is held in a reset state
except the master and slave SMBuses, the control/status registers, and the stacks which continue
to be held in a quasi-reset state and respond to configuration transactions with a retry. The device
remains in this state until the RSTHALT bit is cleared via the slave SMBus. In this mode, an external
agent may read and write any internal control and status registers and may access the external
serial EEPROM via the EEPROMINTF register.
12. Normal device operation begins.