IDT 89HPES34H16, User Manual, Page: 154 / 182

IDT Configuration Registers
PES34H16 User Manual 9 - 62 October 30, 2008
Notes
HPCFGCTL - Hot-Plug Configuration Control (0x408)
Bit
Field
Field
Name
Type
Default
Value
Description
0 IPXAPN RW 0x0
Sticky
Invert Polarity of PxAPN. When this bit is set, the polarity of
the PxAPN input is inverted in all ports.
1 IPXPDN RW 0x0
Sticky
Invert Polarity of PxPDN. When this bit is set, the polarity of
the PxPDN input is inverted in all ports.
2 IPXPFN RW 0x0
Sticky
Invert Polarity of PxPFN. When this bit is set, the polarity of
the PxPFN input is inverted in all ports.
3 IPXMRLN RW 0x0
Sticky
Invert Polarity of PxMRLN. When this bit is set, the polarity
of the PxMRLN input is inverted in all ports.
4 IPXAIN RW 0x0
Sticky
Invert Polarity of PxAIN. When this bit is set, the polarity of
the PxAIN output is inverted in all ports.
5 IPXPIN RW 0x0
Sticky
Invert Polarity of PxPIN. When this bit is set, the polarity of
the PxPIN output is inverted in all ports.
6 IPXPEP RW 0x0
Sticky
Invert Polarity of PxPEP. When this bit is set, the polarity of
the PxPEP output is inverted in all ports.
7 IPXILOCKP RW 0x0
Sticky
Invert Polarity of PxILOCKP. When this bit is set, the polar-
ity of the PxILOCKP output is inverted in all ports.
8 IPXP-
WRGDN
RW 0x0
Sticky
Invert Polarity of PxPWRGDN. When this bit is set, the
polarity of the PxPWRGDN input is inverted in all ports.
10:9 Reserved RW 0x0 Reserved field.
11 MRLP-
WROFF
RW 0x1
Sticky
When the MRL Automatic Power Off. When this bit is set
and the Manual Retention Latch Present (MRLP) bit is set in
the PCI Express Slot Capability (PCIESCAP) register, then
power to the slot is automatically turned off when the MRL
sensor indicates that the MRL is open. This occurs regardless
of the state of the Power Controller Control (PCC) bit in the
PCI Express Slot Control (PCIESCTL) register.
12 RMRL-
WEMIL
RW 0x0
Sticky
Replace MRL Status with EMIL Status. When this bit is set,
the PxMRLN signal inputs are used as electromechanical lock
state inputs.
13 TEMICTL RW 0x0
Sticky
Toggle Electromechanical Interlock Control. When this bit
is cleared, the Electromechanical Interlock (PxILOCKP) out-
put is pulsed for 125 mS when a one is written to the EIC bit in
the PCIESCTL register. When this bit is set, writing a one to
the EIC register inverts the state of the PxILOCKP output.