IDT 89HPES34H16, User Manual, Page: 131 / 182

IDT Configuration Registers
PES34H16 User Manual 9 - 39 October 30, 2008
Notes
ECFGDATA - Extended Configuration Space Access Data (0x0FC)
Advanced Error Reporting (AER) Enhanced Capability
AERCAP - AER Capabilities (0x100)
7:2 REG RW 0x0 Register Number. This field selects the configuration register
number as defined by Section 7.2.2 of the PCI Express Base
Specification, Rev. 1.0a
11:8 EREG RW 0x0 Extended Register Number. This field selects the extended
configuration register number as defined by Section 7.2.2 of
the PCI Express Base Specification, Rev. 1.0a
31:12 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type
Default
Value
Description
31:0 DATA RW 0x0 Configuration Data. A read from this field will return the con-
figuration space register value pointed to by the ECFGADDR
register. A write to this field will update the contents of the
configuration space register pointed to by the ECFGADDR
register with the value written. For both reads and writes, the
byte enables correspond to those used to access this field.
When the ECFGADDR register points to the ECFGDATA reg-
ister, then reads from ECFGDATA return zero and writes are
ignored. When the ECFGADDR register points to itself, writes
to the ECFGDATA register modify the contents of the ECF-
GADDR register.
SMBus reads of this field return a value of zero and SMBus
writes have no effect.
Bit
Field
Field
Name
Type
Default
Value
Description
15:0 CAPID RO 0x1 Capability ID. The value of 0x1 indicates an advanced error
reporting capability structure.
19:16 CAPVER RO 0x1 Capability Version. The value of 0x1. indicates compatibility
with version 1 of the specification.
31:20 NXTPTR RWL 0x180 Next Pointer.
Bit
Field
Field
Name
Type
Default
Value
Description