IDT 89HPES34H16, User Manual, Page: 177 / 182

IDT JTAG Boundary Scan
PES34H16 User Manual 10 - 5 October 30, 2008
Notes
Test Data Register (DR)
The Test Data register contains the following:

Bypass register

Boundary Scan registers

Device ID register
These registers are connected in parallel between a common serial input and a common serial data
output and are described in the following sections. For more detailed descriptions, refer to IEEE Standard
Test Access Port (IEEE Std. 1149.1).
Boundary Scan Registers
This boundary scan chain is connected between JTAG_TDI and JTAG_TDO when EXTEST or
SAMPLE/PRELOAD instructions are selected. Once EXTEST is selected and the TAP controller passes
through the UPDATE-IR state, whatever value that is currently held in the boundary scan register’s output
latches is immediately transferred to the corresponding outputs or output enables.
Therefore, the SAMPLE/PRELOAD instruction must first be used to load suitable values into the
boundary scan cells, so that inappropriate values are not driven out onto the system pins. All of the
boundary scan cells feature a negative edge latch, which guarantees that clock skew cannot cause incor-
rect data to be latched into a cell. The input cells are sample-only cells. The simplified logic configuration is
shown in Figure 10.3.
System Pins CCLKDS I O
CCLKUS I O
MSMBSMODE I O
P01MERGEN I O
P23MERGEN I O
P45MERGEN I O
PERSTN I O
RSTHALT I O
SWMODE[3:0] I —
EJTAG / JTAG JTAG_TCK I —
JTAG_TDI I —
JTAG_TDO O —
JTAG_TMS I —
JTAG_TRST_N I —
1.
I = Input, O = Output
2.
O = Observe, C = Control
Function Pin Name Type
1
Boundary Cell
2
Table 10.2 Boundary Scan Chain (Part 3 of 3)